A Comparative Study of Single-Poly Embedded Flash Memory Disturbance, Program/Erase Speed, Endurance, and Retention Characteristic

• Published in: IEEE transactions on electron devices Vol. 61; no. 11; pp. 3737 - 3743
• Main Authors: Seung-Hwan Song, Jongyeon Kim, Kim, Chris H.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.11.2014; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Couplings; Devices; Disturbances; Durability; Embedded flash (eFlash) memory; embedded nonvolatile memory (eNVM); Endurance; Flash memory (computers); Junctions; Logic; Logic gates; Nonvolatile memory; Semiconductor devices; single-poly eFlash; Transistors; Tunneling; Voltage measurement; single-poly eFlash; Embedded flash (eFlash) memory; embedded nonvolatile memory (eNVM)
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2014.2359388

Single-poly embedded flash (eFlash) memory is a unique category of embedded nonvolatile memory (eNVM) that can be built in a generic logic technology. Several single-poly eFlash cells have been proposed for cost-effective moderate density eNVM applications. However, the optimal cell configuration of single-poly eFlash is still under debate. In this paper, we compared various single-poly eFlash memory structures in terms of disturbance, program/erase speed, endurance, and retention characteristic based on simulated and experimental data from two eFlash test chips fabricated in a generic 65-nm logic process using standard 2.5 V I/O transistors with 5-nm tunnel oxide. We conclude that a 5T eFlash cell structure combining a pMOS coupling device, an NCAP tunneling device, and an nMOS read/program device with two additional pass transistors to support self-boosting is the most attractive option for logic-compatible eNVMs.