A cryogenic SAR ADC for infrared readout circuits

comparatorAbstract： A cryogenic successive approximation register （SAR） analog to digital converter （ADC） is presented. It has been designed to operate in cryogenic infrared readout systems as they are cooled from room temperature to their final cryogenic operation temperature. In order to preserve...

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Bibliographic Details
Published inJournal of semiconductors Vol. 32; no. 11; pp. 152 - 156
Main Author 赵宏亮 赵毅强 张之圣
Format Journal Article
LanguageEnglish
Published IOP Publishing 01.11.2011
Subjects
ADC
Circuits
CMOS工艺
Cryogenics
Infrared
Nonlinearity
Preserves
Sampling
SAR
Semiconductors
Synthetic aperture radar
低温
模数转换器
积分非线性
红外读出
读出电路
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ISSN1674-4926
DOI10.1088/1674-4926/32/11/115015

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Summary:comparatorAbstract： A cryogenic successive approximation register （SAR） analog to digital converter （ADC） is presented. It has been designed to operate in cryogenic infrared readout systems as they are cooled from room temperature to their final cryogenic operation temperature. In order to preserve the circuit＇s performance over this wide temperature range, a temperature-compensated time-based comparator architecture is used in the ADC, which provides a steady performance with ultra low power for extreme temperature （from room temperature down to 77 K） operation. The converter implemented in a standard 0.35 μm CMOS process exhibits 0.64 LSB maximum differential nonlinearity （DNL） and 0.59 LSB maximum integral nonlinearity （1NL）. It achieves 9.3 bit effective number of bits （ENOB） with 200 kS/s sampling rate at 77 K, dissipating 0.23 mW under 3.3 V supply voltage and occupies 0.8 × 0.3 mm^2.
Bibliography:Zhao Hongliang, Zhao Yiqiang, Zhang Zhisheng 1 School of Electronic Information Engineering, Tianjin University, Tianjin 30072, China 2College of Physics, Liaoning University, Shenyang 110036, China
11-5781/TN
comparatorAbstract： A cryogenic successive approximation register （SAR） analog to digital converter （ADC） is presented. It has been designed to operate in cryogenic infrared readout systems as they are cooled from room temperature to their final cryogenic operation temperature. In order to preserve the circuit＇s performance over this wide temperature range, a temperature-compensated time-based comparator architecture is used in the ADC, which provides a steady performance with ultra low power for extreme temperature （from room temperature down to 77 K） operation. The converter implemented in a standard 0.35 μm CMOS process exhibits 0.64 LSB maximum differential nonlinearity （DNL） and 0.59 LSB maximum integral nonlinearity （1NL）. It achieves 9.3 bit effective number of bits （ENOB） with 200 kS/s sampling rate at 77 K, dissipating 0.23 mW under 3.3 V supply voltage and occupies 0.8 × 0.3 mm^2.
cryogenic ADC; low power; successive approximation register; temperature-compensated time-based
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ISSN:1674-4926
DOI:10.1088/1674-4926/32/11/115015