Architecture of Generalized Bit-Flipping Decoding for High-Rate Non-binary LDPC Codes

• Published in: Circuits, systems, and signal processing Vol. 32; no. 2; pp. 727 - 741
• Main Authors: García-Herrero, F., Canet, M. J., Valls, J.
• Format: Journal Article
• Language: English
• Published: Boston SP Birkhäuser Verlag Boston 01.04.2013; Springer Nature B.V
• Subjects: Algorithms; Architecture; Circuits; Circuits and Systems; Codes; Decoding; Devices; Electrical Engineering; Electronics and Microelectronics; Engineering; Field programmable gate arrays; Instrumentation; Noise levels; Signal,Image and Speech Processing; VLSI; Non-binary low-density parity-check (LDPC) codes; VLSI; Decoder; Galois field
• ISSN: 0278-081X; 1531-5878; 1531-5878
• DOI: 10.1007/s00034-012-9481-3

A VLSI architecture for the generalized bit-flipping decoding algorithm for non-binary low-density parity-check codes is proposed in this paper. The tentative decoding steps of the algorithm have been modified to avoid computing and storing a matrix of dimension N ×2 q , for a code ( N , K ) over GF(2 q ), reducing its complexity with a minimal penalization of its performance, less than 0.05 dB compared with the original algorithm. The architecture was synthesized using a 90 nm standard cell library, for the (837,723) non-binary code over GF(2 5 ), requiring 590220 xor gates and achieving a throughput of 89 Mbps. Additionally, it was implemented in a Virtex-VI FPGA device with a cost of 4070 slices and a throughput of 44.6 Mbps.