Single event transient pulse width measurement of 65-nm bulk CMOS circuits

Heavy ion results of a 65-nm CMOS SET pulse width testchip are given. The influences of device threshold voltage, temperature and well separation on pulse width are discussed. Experimental data implied that the low device threshold, high temperature and well speraration would contribute to wider SET...

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Published inJournal of semiconductors Vol. 36; no. 11; pp. 93 - 96
Main Author 岳素格 张晓林 赵馨远
Format Journal Article
LanguageEnglish
Published Chinese Institute of Electronics 01.11.2015
Subjects
65 nm
Circuits
CMOS
CMOS电路
CMOS设置
Devices
Pulse width
pulsewidth
Semiconductors
Separation
SET
Threshold voltage
Thresholds
单事件
多峰现象
瞬态
纳米
脉冲宽度测量
阈值电压
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ISSN1674-4926
DOI10.1088/1674-4926/36/11/115006

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Abstract Heavy ion results of a 65-nm CMOS SET pulse width testchip are given. The influences of device threshold voltage, temperature and well separation on pulse width are discussed. Experimental data implied that the low device threshold, high temperature and well speraration would contribute to wider SET. The multi-peak phenomenon in the distribution of SET pulse width was first observed and its dependence on various factors is also discussed.
AbstractList Heavy ion results of a 65-nm CMOS SET pulse width testchip are given. The influences of device threshold voltage, temperature and well separation on pulse width are discussed. Experimental data implied that the low device threshold, high temperature and well speraration would contribute to wider SET. The multi-peak phenomenon in the distribution of SET pulse width was first observed and its dependence on various factors is also discussed.
Author 岳素格 张晓林 赵馨远
AuthorAffiliation Beij ing University of Aeronautics ＆ Astronautics, Beijing 100191, China Beijing Microelectronics Technology Institute, Beijing 100076, China
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Cites_doi 10.1109/TNS.2008.2007724
10.1109/TNS.2009.2034150
10.1109/TNS.2007.910202
10.1109/TDMR.2006.885589
10.1109/TNS.2009.2033689
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Notes 11-5781/TN
Yue Suge,Zhang Xiaolin,Zhao Xinyuan（ 1.Beijing University of Aeronautics ＆ Astronautics, Beijing 100191, China; 2.Beijing Microelectronics Technology Institute, Beijing 100076, China）
SET; pulsewidth; 65 nm
Heavy ion results of a 65-nm CMOS SET pulse width testchip are given. The influences of device threshold voltage, temperature and well separation on pulse width are discussed. Experimental data implied that the low device threshold, high temperature and well speraration would contribute to wider SET. The multi-peak phenomenon in the distribution of SET pulse width was first observed and its dependence on various factors is also discussed.
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Snippet Heavy ion results of a 65-nm CMOS SET pulse width testchip are given. The influences of device threshold voltage, temperature and well separation on pulse...
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SubjectTerms 65 nm
Circuits
CMOS
CMOS电路
CMOS设置
Devices
Pulse width
pulsewidth
Semiconductors
Separation
SET
Threshold voltage
Thresholds
单事件
多峰现象
瞬态
纳米
脉冲宽度测量
阈值电压
Title Single event transient pulse width measurement of 65-nm bulk CMOS circuits
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