Analysis and design of a 1.8-2.7 GHz tunable 8-band TDD LTE receiver front-end

This paper describes the analysis and design of a 0.13 #m CMOS tunable receiver front-end that supports 8 TDD LTE bands, covering the 1.8-2.7 GHz frequency band and supporting the 5/10/15/20 MHz bandwidth and QPSK/16QAM/64QAM modulation schemes. The novel zero-IF receiver core consists of a tunable...

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Published inJournal of semiconductors Vol. 32; no. 5; pp. 104 - 110
Main Author 王肖 王玉吉 王伟威 常学贵 闫姗 谈熙 闵昊
Format Journal Article
LanguageEnglish
Published IOP Publishing 01.05.2011
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ISSN1674-4926
DOI10.1088/1674-4926/32/5/055006

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Summary:This paper describes the analysis and design of a 0.13 #m CMOS tunable receiver front-end that supports 8 TDD LTE bands, covering the 1.8-2.7 GHz frequency band and supporting the 5/10/15/20 MHz bandwidth and QPSK/16QAM/64QAM modulation schemes. The novel zero-IF receiver core consists of a tunable narrow- band variable gain low-noise amplifier (LNA), a current commutating passive down-conversion mixer with a 2nd order low pass trans-impedance amplifier, an LO divider, a rough gain step variable gain pre-amplifier, a tunable 4th order Chebyshev channel select active-RC low pass filter with cutoff frequency calibration circuit and a fine gain step variable gain amplifier. The LNA can be tuned by reconfiguring the output parallel LC tank to the responding frequency band, eliminating the fixed center frequency multiple LNA array for a multi-mode receiver. The large various gain range and bandwidth of the analog baseband can also be tuned by digital configuration to satisfy the specification requirement of various bandwidth and modulation schemes. The test chip is implemented in an SMIC 0.13μm 1PSM CMOS process. The full receiver achieves 4.6 dB NF, -14.5 dBm out of band IIP3, 30-94 dB gain range and consumes 54 mA with a 1.2 V power supply.
Bibliography:This paper describes the analysis and design of a 0.13 #m CMOS tunable receiver front-end that supports 8 TDD LTE bands, covering the 1.8-2.7 GHz frequency band and supporting the 5/10/15/20 MHz bandwidth and QPSK/16QAM/64QAM modulation schemes. The novel zero-IF receiver core consists of a tunable narrow- band variable gain low-noise amplifier (LNA), a current commutating passive down-conversion mixer with a 2nd order low pass trans-impedance amplifier, an LO divider, a rough gain step variable gain pre-amplifier, a tunable 4th order Chebyshev channel select active-RC low pass filter with cutoff frequency calibration circuit and a fine gain step variable gain amplifier. The LNA can be tuned by reconfiguring the output parallel LC tank to the responding frequency band, eliminating the fixed center frequency multiple LNA array for a multi-mode receiver. The large various gain range and bandwidth of the analog baseband can also be tuned by digital configuration to satisfy the specification requirement of various bandwidth and modulation schemes. The test chip is implemented in an SMIC 0.13μm 1PSM CMOS process. The full receiver achieves 4.6 dB NF, -14.5 dBm out of band IIP3, 30-94 dB gain range and consumes 54 mA with a 1.2 V power supply.
long-term evolution; receiver; tunable; CMOS
11-5781/TN
Wang Xiao, Wang Yuji, Wang Weiwei, Chang Xuegui, Yan Na, Tan Xi, Min Hao(State Key Laboratory ofASIC & System, Fudan University, Shanghai 200433, China)
ObjectType-Article-2
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ISSN:1674-4926
DOI:10.1088/1674-4926/32/5/055006