Formal Verification of Integer Multiplier Circuits Using Binary Decision Diagrams

• Published in: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Vol. 42; no. 4; pp. 1365 - 1378
• Main Authors: Kumar, Jitendra, Miyasaka, Yukio, Srivastava, Asutosh, Fujita, Masahiro
• Format: Journal Article
• Language: English; Japanese
• Published: New York IEEE 01.04.2023; Institute of Electrical and Electronics Engineers (IEEE); The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Adder trees; Adders; algebraic backward rewriting; Algorithms; Binary decision diagrams; binary decision diagrams (BDDs); Circuit diagrams; Complexity; Computer algebra; Computer bugs; Cryptography; Digital signal processing; Embedded systems; Equivalence; Error analysis; error tolerance analysis; Formal verification; Integers; Mathematical analysis; Multimedia; multiplier verification; Multipliers; Optimization; Polynomials; Signal processing algorithms; Tolerance analysis; Verification
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/TCAD.2022.3192176

Multiplier circuit covers a more extensive area of embedded system application in digital signal processing, cryptography, and multimedia. Nonstandard implementations and custom optimization are being done to reduce the size of multipliers. The circuit became prone to a buggy, and hence the demand for verification increased. Formal verification methods, such as satisfiability (SAT), symbolic computer algebra (SCA), and binary decision diagrams (BDDs) have made massive progress over the last few decades. However, these methods are insufficient to verify the optimized multipliers. SAT-based equivalence checking is computationally expensive. SCA-based backward rewriting is limited to algebraic-friendly multipliers. The complexity of BDDs is exponential with the input size. Although, by allowing an additional variable method, the size of the BDD is limited to 4th degree polynomial of the number of the inputs, this method is not explored to verify optimized multipliers. This article focus on verifying integer multipliers with diverse architectures. We propose an algorithm for the direct construction of BDDs without traversing circuits and generate BDDs up to 1024 bits. We utilize the additional variable method and constructing BDDs using high-to-low variable ordering. We reduce the complexity of BDD size to a 3rd degree polynomial. We generate BDDs and verify the multipliers with various architectures up to 64 bits. We propose a method to verify optimized multipliers by checking equivalence and verifying up to 32-bits optimized multipliers. We do the error tolerance analysis of our approach by inserting bugs in a circuit at various locations.