A Single-Loop SS-LMS Algorithm With Single-Ended Integrating DFE Receiver for Multi-Drop DRAM Interface

• Published in: IEEE journal of solid-state circuits Vol. 46; no. 9; pp. 2053 - 2063
• Main Authors: Chi, Hyung-Joon, Lee, Jae-Seung, Jeon, Seong-Hwan, Bae, Seung-Jun, Sohn, Young-Soo, Sim, Jae-Yoon, Park, Hong-June
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.09.2011; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Applied sciences; Chips; Circuits; Clocks; CMOS; Decision feedback equalization; Decision feedback equalizers; Delay; Design. Technologies. Operation analysis. Testing; DFE; DRAM interface; Dynamic random access memory; Electric potential; Electronic equipment and fabrication. Passive components, printed wiring boards, connectics; Electronics; equalizer; Exact sciences and technology; Integrated circuits; Integrated circuits by function (including memories and processors); integration; ISI; multi-drop bus; Noise; Preamplifiers; Receivers; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; single-ended signaling; SS-LMS; Synchronization; Voltage; DFE; Random access memory; multi-drop bus; Decision feedback equalizers; SS-LMS; Offset voltage; Decision feedback equalization; Preamplifier; Non volatile memory; Feedback; Complementary MOS technology; equalizer; Design for environment; ISI; Dynamic random access memory; Receiver; Bus(channel); single-ended signaling; Intersymbol interference; Interconnection; Integrated circuit; integration; DRAM interface; Ecological approach; Least mean squares methods
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2011.2136590

A 3.8 Gb/s multi-drop single-ended integrating DFE (IDFE) receiver is implemented in a 0.18 um CMOS by using a single-loop LMS-algorithm to find the DFE coefficients automatically. Initially, a preamble input data pattern ('1101') is applied to the main IDFE circuit to determine the DFE coefficients, while a fixed input data pattern ('1111') is applied to the replica IDFE circuit. The difference between the outputs of the two IDFE circuits is used in the feedback loop to determine the DFE coefficients. The reference voltage (Vref) of preamplifier is generated inside chip by a Vref loop to reduce the effect of the external noise and the input offset voltage of preamplifier and IDFE circuits and also to track the mid-level of the input data swing in spite of process variations of TX chips. An integrating deskew scheme with a minimum overhead is introduced. 2-drop and 4-drop DRAM channels are tested. The maximum data rate was increased from 1.0 Gb/s to 2.6 Gb/s by DFE in the heavily loaded 4-drop interface, from 3.5 Gb/s to 3.8 Gb/s by DFE in the 2-drop interface.