A Single-Chip 10-Band WCDMA/HSDPA 4-Band GSM/EDGE SAW-less CMOS Receiver With DigRF 3G Interface and 90 dBm IIP2

This paper describes the design and performance of a 90 nm CMOS SAW-less receiver with DigRF interface that supports 10 WCDMA bands (I, II, III, IV, V, VI, VIII, IX, X, XI) and 4 GSM bands (GSM850, EGSM900, DCS1800, PCS1900). The receiver is part of a single-chip SAW-less transceiver reference platf...

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Bibliographic Details
Published inIEEE journal of solid-state circuits Vol. 44; no. 3; pp. 718 - 739
Main Authors Kaczman, D., Shah, M., Alam, M., Rachedine, M., Cashen, D., Lu Han, Raghavan, A.
Format Journal Article
LanguageEnglish
Published New York, NY IEEE 01.03.2009
Institute of Electrical and Electronics Engineers
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects
EVM
GSM
GSM
3G
EVM
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ISSN0018-9200
1558-173X
DOI10.1109/JSSC.2009.2013762

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Summary:This paper describes the design and performance of a 90 nm CMOS SAW-less receiver with DigRF interface that supports 10 WCDMA bands (I, II, III, IV, V, VI, VIII, IX, X, XI) and 4 GSM bands (GSM850, EGSM900, DCS1800, PCS1900). The receiver is part of a single-chip SAW-less transceiver reference platform IC for mass-market smartphones, which has been designed to meet Category 10 HSDPA (High Speed Downlink Packet Access) requirements. The novel receiver core consists of a single-stage transconductance amplifier (TCA) with large gain control range, a current commutating passive mixer enhanced for automatic on chip IIP2 calibration with 25% duty-cycle LO injection and threshold adjust, and current-input complex Direct Coupled Filter (DCF). The low noise TCAs are designed without inductive loads to save area. A self-contained on chip automatic IIP2 calibration system with algorithm routine, implemented in firmware, is used to optimize IIP2 performance. This topology eliminates the external LNA, inter-stage SAW filter and transimpedance amplifier (TZA) in conventional WCDMA designs and results in current drain and die area savings as well as improved noise. The 25% duty-cycle LO injection, with threshold adjustment, into a current driven passive double-balanced mixer results in 3 dB additional gain, lower noise figure and lower intermodulation distortion. Large signal blocking and 1/f noise performance are improved significantly by eliminating the 0 and 180deg LO signal crossover at the mixer. The full receiver achieves 2.2 dB/2.39 dB simplex/duplex NF (with - 24.5 dBm TX leakage), > 90 dBm complex two-tone IIP2, 60 dB gain and - 1/+ 5 dBm half/full-duplex image IIP3. The receiver core consumes only 15.1 mA from a 1.5 V supply.
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ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2009.2013762