The design and hardware implementation of a low-power real-time seizure detection algorithm

• Published in: Journal of neural engineering Vol. 6; no. 5; p. 056005
• Main Authors: Raghunathan, Shriram, Gupta, Sumeet K, Ward, Matthew P, Worth, Robert M, Roy, Kaushik, Irazoqui, Pedro P
• Format: Journal Article
• Language: English
• Published: England IOP Publishing 01.10.2009
• Subjects: Algorithms; Animals; Diagnosis, Computer-Assisted - instrumentation; Diagnosis, Computer-Assisted - methods; Electric Power Supplies; Electroencephalography - instrumentation; Electroencephalography - methods; Equipment Design; Equipment Failure Analysis; Female; Rats; Rats, Long-Evans; Reproducibility of Results; Seizures - diagnosis; Sensitivity and Specificity; Signal Processing, Computer-Assisted - instrumentation
• ISSN: 1741-2552; 1741-2560; 1741-2552
• DOI: 10.1088/1741-2560/6/5/056005

Epilepsy affects more than 1% of the world's population. Responsive neurostimulation is emerging as an alternative therapy for the 30% of the epileptic patient population that does not benefit from pharmacological treatment. Efficient seizure detection algorithms will enable closed-loop epilepsy prostheses by stimulating the epileptogenic focus within an early onset window. Critically, this is expected to reduce neuronal desensitization over time and lead to longer-term device efficacy. This work presents a novel event-based seizure detection algorithm along with a low-power digital circuit implementation. Hippocampal depth-electrode recordings from six kainate-treated rats are used to validate the algorithm and hardware performance in this preliminary study. The design process illustrates crucial trade-offs in translating mathematical models into hardware implementations and validates statistical optimizations made with empirical data analyses on results obtained using a real-time functioning hardware prototype. Using quantitatively predicted thresholds from the depth-electrode recordings, the auto-updating algorithm performs with an average sensitivity and selectivity of 95.3 +/- 0.02% and 88.9 +/- 0.01% (mean +/- SE(alpha = 0.05)), respectively, on untrained data with a detection delay of 8.5 s [5.97, 11.04] from electrographic onset. The hardware implementation is shown feasible using CMOS circuits consuming under 350 nW of power from a 250 mV supply voltage from simulations on the MIT 180 nm SOI process.