T-Gate Fabrication of InP-Based HEMTs Using PMGI/ZEP520A/PMGI/ZEP520A Stacked Resist

PMGI/ZEP520A/PMGI/ZEP520 A fourlayer resist stack is firstly proposed for T-gates fabrication of InP-based High electron mobility transistors(HEMTs).Gate-head and gate-foot are exposed in single-step Electron beam lithography(EBL), which avoids alignment deviation by automatic self-alignment. The ne...

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Bibliographic Details
Published inChinese Journal of Electronics Vol. 25; no. 3; pp. 448 - 452
Main Authors Zhong, Yinghui, Zang, Huaping, Wang, Haili, Sun, Shuxiang, Li, Kaikai, Ding, Peng, Jin, Zhi
Format Journal Article
LanguageEnglish
Published Published by the IET on behalf of the CIE 01.05.2016
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Online AccessGet full text
ISSN1022-4653
2075-5597
DOI10.1049/cje.2016.05.009

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Summary:PMGI/ZEP520A/PMGI/ZEP520 A fourlayer resist stack is firstly proposed for T-gates fabrication of InP-based High electron mobility transistors(HEMTs).Gate-head and gate-foot are exposed in single-step Electron beam lithography(EBL), which avoids alignment deviation by automatic self-alignment. The newly introduced PMGI at the bottom greatly improves the adhesiveness of ZEP520 A resist with the substrate. The optimal gate-foot length reaches 101 nm for a design of 50 nm gate footprint pattern, and which can be improved to be 66.8nm for 30 nm gate footprint pattern. Finally, Tgates in nanometer regime have been successfully incorporated into InP-based HEMTs fabrication. Benefiting from both the narrow gate-foot and the reduced parasitic gatecapacitance by single-step EBL technique with the fourlayer resist stack, the fabricated devices with gate-foot length of 101 nm demonstrate excellent DC and RF performances: the maximum extrinsic transconductance, the current-gain cutoff frequency and maximum oscillation frequency are 1051 m S/mm, 249 GHz and 415 GHz, respectively.
Bibliography:PMGI/ZEP520A/PMGI/ZEP520 A fourlayer resist stack is firstly proposed for T-gates fabrication of InP-based High electron mobility transistors(HEMTs).Gate-head and gate-foot are exposed in single-step Electron beam lithography(EBL), which avoids alignment deviation by automatic self-alignment. The newly introduced PMGI at the bottom greatly improves the adhesiveness of ZEP520 A resist with the substrate. The optimal gate-foot length reaches 101 nm for a design of 50 nm gate footprint pattern, and which can be improved to be 66.8nm for 30 nm gate footprint pattern. Finally, Tgates in nanometer regime have been successfully incorporated into InP-based HEMTs fabrication. Benefiting from both the narrow gate-foot and the reduced parasitic gatecapacitance by single-step EBL technique with the fourlayer resist stack, the fabricated devices with gate-foot length of 101 nm demonstrate excellent DC and RF performances: the maximum extrinsic transconductance, the current-gain cutoff frequency and maximum oscillation frequency are 1051 m S/mm, 249 GHz and 415 GHz, respectively.
T-gate High electron mobility transistors(HEMTs) InP ZEP520A Electron beam lithography(EBL)
ISSN:1022-4653
2075-5597
DOI:10.1049/cje.2016.05.009