A Magnetometer-Only Attitude Determination Strategy for Small Satellites: Design of the Algorithm and Hardware-in-the-Loop Testing

• Published in: Aerospace Vol. 7; no. 1; p. 3
• Main Authors: Carletta, Stefano, Teofilatto, Paolo, Farissi, M.
• Format: Journal Article
• Language: English
• Published: Basel MDPI AG 01.01.2020
• Subjects: Accuracy; Airborne/spaceborne computers; Algorithms; attitude determination; Butterworth filters; Complexity; Cubesat; faddeev algorithm; Field programmable gate arrays; Geomagnetic field; Geomagnetism; Hardware-in-the-loop simulation; hil; Kalman filters; Low pass filters; magnetometer-only; Magnetometers; Nanosatellites; Numerical analysis; Robustness (mathematics); Satellite tracking; Satellites; Sensors; Small satellites; Spacecraft; Spacecraft tracking; systolic array; Three axis
• ISSN: 2226-4310; 2226-4310
• DOI: 10.3390/aerospace7010003

Attitude determination represents a fundamental task for spacecraft. Achieving this task on small satellites, and nanosatellites in particular, is further challenging, because the limited power and computational resources available on-board, together with the low development budget, set strict constraints on the selection of the sensors and the complexity of the algorithms. Attitude determination is obtained here from the only measurements of a three-axis magnetometer and a model of the Geomagnetic field, stored on the on-board computer. First, the angular rates are estimated and processed using a second-order low-pass Butterworth filter, then they are used as an input, along with Geomagnetic field data, to estimate the attitude matrix using an unsymmetrical TRIAD. The computational efficiency is enhanced by arranging complex matrix operations into a form of the Faddeev algorithm, which is implemented using systolic array architecture on the FPGA core of a CubeSat on-board computer. The performance and the robustness of the algorithm are evaluated by means of numerical analyses in MATLAB Simulink, showing pointing and angular rate accuracy below 10° and 0.2°/s. The algorithm implemented on FPGA is verified by Hardware-in-the-loop simulation, confirming the results from numerical analyses and efficiency.