Built-in redundancy analysis for memory yield improvement

• Published in: IEEE transactions on reliability Vol. 52; no. 4; pp. 386 - 399
• Main Authors: Huang, Chih-Tsun, Wu, Chi-Feng, Li, Jin-Fu, Wu, Cheng-Wen
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.12.2003; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithm design and analysis; Algorithms; Built-in self-test; Chips (memory devices); Circuit faults; Circuit simulation; Circuits; Costs; Density; Design engineering; Electrostatic precipitators; Local optimization; Random access memory; Redundancy; Repair; Studies; Testing; Very large scale integration
• ISSN: 0018-9529; 1558-1721
• DOI: 10.1109/TR.2003.821925

With the advance of VLSI technology, the capacity and density of memories is rapidly growing. The yield improvement and testing issues have become the most critical challenges for memory manufacturing. Conventionally, redundancies are applied so that the faulty cells can be repairable. Redundancy analysis using external memory testers is becoming inefficient as the chip density continues to grow, especially for the system chip with large embedded memories. This paper presents three redundancy analysis algorithms which can be implemented on-chip. Among them, two are based on the local-bitmap idea: the local repair-most approach is efficient for a general spare architecture, and the local optimization approach has the best repair rate. The essential spare pivoting technique is proposed to reduce the control complexity. Furthermore, a simulator has been developed for evaluating the repair efficiency of different algorithms. It is also used for determining certain important parameters in redundancy design. The redundancy analysis circuit can easily be integrated with the built-in self-test circuit.