An FPGA-based approach to the automatic generation of VHDL code for industrial control systems applications: A case study of MSOGIs implementation

• Published in: Mathematics and computers in simulation Vol. 91; pp. 178 - 192
• Main Authors: Martín, P., Bueno, E., Rodríguez, Fco. J., Machado, O., Vuksanovic, B.
• Format: Journal Article
• Language: English
• Published: Elsevier B.V 01.05.2013
• Subjects: Control systems; FPGA-based systems; Scheduling; System-level specification; Xilinx System Generator; System-level specification; Control systems; Scheduling; Xilinx System Generator; FPGA-based systems
• ISSN: 0378-4754; 1872-7166
• DOI: 10.1016/j.matcom.2012.07.004

► FPGAs are a suitable alternative for industrial control systems implementations. ► It is essential to reduce the gap between the control system designers and FPGA designers. ► We present a methodology that bridges the gap. ► System level tools can yield discouraging results in terms of resources utilized. ► A tool is designed to support the methodology that enhances efficiency and productivity. When used for specifying control systems, system level design tools such as Xilinx System Generator (XSG) allows the use of Simulink for designs based on Field Programmable Gate Arrays (FPGAs). This increases productivity by reducing the wide gap between control system designers and FPGA-based implementations. However, there is still a need for new methods to bridge the gap since a direct implementation from XSG may not be an optimal solution when constraints are imposed. This is particularly true for resource-dominated circuits, where the number of operational units exceed the number of available resources. This paper presents both a methodology and a tool aimed at automatically reducing the required resources, in particular in systems where the required sampling period is greater than the computation time delay. An automatic process of converting XSG specifications into efficient Very High Speed Integrated Circuit Hardware Description Language (VHDL) code is described. The process mainly involves customized fixed-point hardware definition, Data Flow Graph (DFG) extraction, resource-constrained and latency-constrained scheduling and VHDL specification of the system, inter alia. This solution considerably improves on the results obtained by XSG.