Concurrent Error Detection in Finite-Field Arithmetic Operations Using Pipelined and Systolic Architectures

• Published in: IEEE transactions on computers Vol. 58; no. 11; pp. 1553 - 1567
• Main Authors: Bayat-Sarmadi, S., Hasan, M.A.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.11.2009; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Arithmetic; Computer architecture; concurrent error correction (CEC); concurrent error detection (CED); Decoding; dual basis; Encoding; Error correction; Error detection; Faults; Finite-field operations; Multipliers; Niobium; normal basis; Optimization; Pipeline processing; pipelined architectures; polynomial basis; Polynomials; Registers; Systolic arrays
• ISSN: 0018-9340; 1557-9956
• DOI: 10.1109/TC.2009.62

In this work, we consider detection of errors in polynomial, dual, and normal bases arithmetic operations. Error detection is performed by recomputing with the shifted operand method, while the operation unit is in use. This scheme is efficient for pipelined architectures, particularly systolic arrays. Additionally, one semisystolic multiplier for each of the polynomial, dual, type I, and type II optimal normal bases is presented. The results show that for having better or similar space and time overheads compared to a number of related previous work, the multipliers have generally a higher error-detection capability, e.g., the error-detection capability of the RESO-based scheme for single and multiple stuck-at faults in a polynomial basis multiplier is 100 percent. Finally, we also comment on how RESO can be used for concurrent error correction to deal with transient faults.