Tunnel Field-Effect Transistors: Prospects and Challenges

• Published in: IEEE journal of the Electron Devices Society Vol. 3; no. 3; pp. 88 - 95
• Main Authors: Avci, Uygar E., Morris, Daniel H., Young, Ian A.
• Format: Journal Article
• Language: English
• Published: IEEE 01.05.2015
• Subjects: Doping; Logic gates; MOSFET; Silicon; steep-slope; TFET; Tunneling; Tunnel field-effect transistor (TFET); Steep-slope
• ISSN: 2168-6734; 2168-6734
• DOI: 10.1109/JEDS.2015.2390591

The tunnel field-effect transistor (TFET) is considered a future transistor option due to its steep-slope prospects and the resulting advantages in operating at low supply voltage (V DD ). In this paper, using atomistic quantum models that are in agreement with experimental TFET devices, we are reviewing TFETs prospects at L G = 13 nm node together with the main challenges and benefits of its implementation. Significant power savings at iso-performance to CMOS are shown for GaSb/InAs TFET, but only for performance targets which use lower than conventional V DD . Also, P-TFET current-drive is between 1× to 0.5× of N-TFET, depending on choice of I OFF and V DD . There are many challenges to realizing TFETs in products, such as the requirement of high quality III-V materials and oxides with very thin body dimensions, and the TFET's layout density and reliability issues due to its source/drain asymmetry. Yet, extremely parallelizable products, such as graphics cores, show the prospect of longer battery life at a cost of some chip area.