Ant Colony Heuristic for Mapping and Scheduling Tasks and Communications on Heterogeneous Embedded Systems

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems Vol. 29; no. 6; pp. 911 - 924
• Main Authors: Ferrandi, Fabrizio, Lanzi, Pier Luca, Pilato, Christian, Sciuto, Donatella, Tumeo, Antonino
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.06.2010; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Ant colony optimization; Ant colony optimization (ACO); Approximation algorithms; Architecture; Colonies; communications; Design engineering; Embedded system; Field programmable gate arrays; field programmable gate arrays (FPGA); Genetic algorithms; Heuristic; Mapping; Mathematical models; multiprocessors; Operations research; Optimization; Processor scheduling; Scheduling; Scheduling algorithm; Simulated annealing; Space exploration; Stochastic processes; Studies; Tasks
• ISSN: 0278-0070; 1937-4151; 1937-4151
• DOI: 10.1109/TCAD.2010.2048354

To exploit the power of modern heterogeneous multiprocessor embedded platforms on partitioned applications, the designer usually needs to efficiently map and schedule all the tasks and the communications of the application, respecting the constraints imposed by the target architecture. Since the problem is heavily constrained, common methods used to explore such design space usually fail, obtaining low-quality solutions. In this paper, we propose an ant colony optimization (ACO) heuristic that, given a model of the target architecture and the application, efficiently executes both scheduling and mapping to optimize the application performance. We compare our approach with several other heuristics, including simulated annealing, tabu search, and genetic algorithms, on the performance to reach the optimum value and on the potential to explore the design space. We show that our approach obtains better results than other heuristics by at least 16% on average, despite an overhead in execution time. Finally, we validate the approach by scheduling and mapping a JPEG encoder on a realistic target architecture.