Pipelined H-trees for high-speed clocking of large integrated systems in presence of process variations

• Published in: IEEE transactions on very large scale integration (VLSI) systems Vol. 5; no. 2; pp. 161 - 174
• Main Authors: Nekili, M., Bois, G., Savaria, Y.
• Format: Journal Article
• Language: English
• Published: Piscataway, NJ IEEE 01.06.1997; Institute of Electrical and Electronics Engineers
• Subjects: Applied sciences; Clocks; CMOS technology; Delay; Design. Technologies. Operation analysis. Testing; Digital systems; Electronics; Exact sciences and technology; Frequency; Integrated circuits; Inverters; Logic; Predictive models; Semiconductor device modeling; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Upper bound; Pipeline processor; Integrated circuit; Theoretical study; Tree; Digital circuit; Clock; Computer aided design
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/92.585214

This paper addresses the problem of clocking large high-speed digital systems, as well as deterministic skew modeling, a related problem. In order to provide a reliable skew model, and to avoid the frequency limitation, we propose a novel approach that distributes the clock with an H-tree, whose branches are composed of minimum-sized inverters rather than metal. With such a structure, we obtain the highest clocking rate achievable with a given technology. Indeed, clock rates around 1 GHz are possible with a 1.2 /spl mu/m CMOS technology. From the skew modeling standpoint, we derive an analytic expression of the skew between two leaves of the H-tree, which we consider to be the difference in root-to-leaf delay pairs. The skew upper bound obtained has an order of complexity which, with respect to the H-tree size D, is the same as the one that may be derived from the Fisher and Kung model for both side-to-side and neighbor-to-neighbor communications, i.e., a /spl Omega/(D/sup 2/), whereas, the Steiglitz and Kugelmass probabilistic model predicts /spl Theta/(D/spl times//spl radic/LogD). In an H-tree implemented with metallic lines, the leaf-to-leaf skew is obviously bounded by the delay between the root and the leaves. However, with the logic based H-tree proposed here, we arrive at a nonobvious result, which states that the leaf-to-leaf skew grows faster than the root-to-leaf delay in presence of a uniform transistor time constant gradient. This paper also proposes generalizations of the skew model to (1) the case of chips in a wafer subject to a smooth, but nonuniform gradient and (2) the case of H-tree configurations mixing logic and interconnections; in this respect, this paper covers the H-tree configurations based on the combination of logic and interconnections.