Deadlock-free adaptive 3D network-on-chips routing algorithm with repetitive turn concept

With the emergence of a large number of multi-core systems, many 3D routing schemes have been developed for network-on-chips (NoCs) in order to obtain low overhead and high-performance. Nevertheless, it is difficult to possess these characteristics for contemporary 3D routing algorithms. This study...

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Published inIET communications Vol. 14; no. 11; pp. 1783 - 1792
Main Authors Cai, Yuan, Xiang, Dong, Ji, Xiang
Format Journal Article
LanguageEnglish
Published The Institution of Engineering and Technology 14.07.2020
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ISSN1751-8628
1751-8636
DOI10.1049/iet-com.2019.0269

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Abstract With the emergence of a large number of multi-core systems, many 3D routing schemes have been developed for network-on-chips (NoCs) in order to obtain low overhead and high-performance. Nevertheless, it is difficult to possess these characteristics for contemporary 3D routing algorithms. This study presents a new routing algorithm for 3D stacked NoCs based on the repetitive turn concept. The authors propose the high-performance minimum pressure turn model (MPTM) routing algorithm that can be applied to a 3D case. Repetitive prohibited turns are spread in the row and column of the planes and vertical direction in the MPTM routing algorithm with no virtual channels. Besides, the MPTM routing algorithm has minimum routing pressure by exploring the whole 3D space. Considering network average latency and throughput, the results acquired show that the MPTM scheme improves performance over existing work.
AbstractList With the emergence of a large number of multi‐core systems, many 3D routing schemes have been developed for network‐on‐chips (NoCs) in order to obtain low overhead and high‐performance. Nevertheless, it is difficult to possess these characteristics for contemporary 3D routing algorithms. This study presents a new routing algorithm for 3D stacked NoCs based on the repetitive turn concept. The authors propose the high‐performance minimum pressure turn model (MPTM) routing algorithm that can be applied to a 3D case. Repetitive prohibited turns are spread in the row and column of the planes and vertical direction in the MPTM routing algorithm with no virtual channels. Besides, the MPTM routing algorithm has minimum routing pressure by exploring the whole 3D space. Considering network average latency and throughput, the results acquired show that the MPTM scheme improves performance over existing work.
Author Ji, Xiang
Cai, Yuan
Xiang, Dong
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Issue 11
Keywords 3D stacked NoCs
network-on-chip
minimum routing pressure
network routing
network average latency
network throughput
repetitive turn concept
MPTM routing algorithm
repetitive prohibited turns
multicore systems
deadlock-free adaptive 3D network-on-chip routing algorithm
high-performance minimum pressure turn model routing algorithm
three-dimensional integrated circuits
contemporary 3D routing algorithms
3D routing schemes
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Snippet With the emergence of a large number of multi-core systems, many 3D routing schemes have been developed for network-on-chips (NoCs) in order to obtain low...
With the emergence of a large number of multi‐core systems, many 3D routing schemes have been developed for network‐on‐chips (NoCs) in order to obtain low...
SourceID crossref
wiley
iet
SourceType Enrichment Source
Index Database
Publisher
StartPage 1783
SubjectTerms 3D routing schemes
3D stacked NoCs
contemporary 3D routing algorithms
deadlock‐free adaptive 3D network‐on‐chip routing algorithm
high‐performance minimum pressure turn model routing algorithm
minimum routing pressure
MPTM routing algorithm
multicore systems
network average latency
network routing
network throughput
network‐on‐chip
repetitive prohibited turns
repetitive turn concept
Research Article
three‐dimensional integrated circuits
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Title Deadlock-free adaptive 3D network-on-chips routing algorithm with repetitive turn concept
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