Deadlock-free adaptive 3D network-on-chips routing algorithm with repetitive turn concept
With the emergence of a large number of multi-core systems, many 3D routing schemes have been developed for network-on-chips (NoCs) in order to obtain low overhead and high-performance. Nevertheless, it is difficult to possess these characteristics for contemporary 3D routing algorithms. This study...
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| Published in | IET communications Vol. 14; no. 11; pp. 1783 - 1792 |
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| Main Authors | , , |
| Format | Journal Article |
| Language | English |
| Published |
The Institution of Engineering and Technology
14.07.2020
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| Subjects | |
| Online Access | Get full text |
| ISSN | 1751-8628 1751-8636 |
| DOI | 10.1049/iet-com.2019.0269 |
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| Summary: | With the emergence of a large number of multi-core systems, many 3D routing schemes have been developed for network-on-chips (NoCs) in order to obtain low overhead and high-performance. Nevertheless, it is difficult to possess these characteristics for contemporary 3D routing algorithms. This study presents a new routing algorithm for 3D stacked NoCs based on the repetitive turn concept. The authors propose the high-performance minimum pressure turn model (MPTM) routing algorithm that can be applied to a 3D case. Repetitive prohibited turns are spread in the row and column of the planes and vertical direction in the MPTM routing algorithm with no virtual channels. Besides, the MPTM routing algorithm has minimum routing pressure by exploring the whole 3D space. Considering network average latency and throughput, the results acquired show that the MPTM scheme improves performance over existing work. |
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| ISSN: | 1751-8628 1751-8636 |
| DOI: | 10.1049/iet-com.2019.0269 |