Evaluation of stereo correspondence algorithms and their implementation on FPGA

• Published in: Journal of systems architecture Vol. 60; no. 1; pp. 22 - 31
• Main Authors: Colodro-Conde, Carlos, Toledo-Moreo, F. Javier, Toledo-Moreo, Rafael, Martínez-Álvarez, J. Javier, Garrigós Guerrero, Javier, Ferrández-Vicente, J. Manuel
• Format: Journal Article
• Language: English
• Published: Amsterdam Elsevier B.V 01.01.2014; Elsevier Sequoia S.A
• Subjects: Algorithms; Architecture (computers); Computer architecture; Embedded and real-time systems; Embedded systems; Field programmable gate arrays; FPGA; Hardware; Mathematical analysis; Optical industry; Real time; Stereo vision; Studies; Tradeoffs; Vision systems; FPGA; Embedded and real-time systems; Stereo vision
• ISSN: 1383-7621; 1873-6165
• DOI: 10.1016/j.sysarc.2013.11.006

The accuracy of stereo vision has been considerably improved in the last decade, but real-time stereo matching is still a challenge for embedded systems where the limited resources do not permit fast operation of sophisticated approaches. This work presents an evaluation of area-based algorithms used for calculating distance in stereoscopic vision systems, their hardware architectures for implementation on FPGA and the cost of their accuracies in terms of FPGA hardware resources. The results show the trade-off between the quality of such maps and the hardware resources which each solution demands, so they serve as a guide for implementing stereo correspondence algorithms in real-time processing systems.