FPGA based unified architecture for public key and private key cryptosystems

• Published in: Frontiers of Computer Science Vol. 7; no. 3; pp. 307 - 316
• Main Authors: WANG, Yi, LI, Renfa
• Format: Journal Article
• Language: English
• Published: Heidelberg Higher Education Press 01.06.2013; SP Higher Education Press; Springer Nature B.V
• Subjects: AES; Algorithms; Arithmetic and logic units; arithmetic unit; Computation; Computer Science; Computer systems; cryptographic algorithms; Cryptography; Curves; Digital signatures; ECC; Embedded systems; Encryption; Field programmable gate arrays; Fields (mathematics); FPGA; Hardware; high radix; Research Article; RSA; Security; signed-digit number; RSA; high radix; ECC; signed-digit number; FPGA; cryptographic algorithms; arithmetic unit; AES
• ISSN: 2095-2228; 2095-2236
• DOI: 10.1007/s11704-013-2187-2

Recently, security in embedded system arises attentions because of modern electronic devices need cautiously either exchange or communicate with the sensitive data. Although security is classical research topic in worldwide communication, the researchers still face the problems of how to deal with these resource constraint devices and enhance the features of assurance and certification. Therefore, some computations of cryptographic algorithms are built on hardware platforms, such as field program gate arrays (FPGAs). The commonly used cryptographic algorithms for digital signature algorithm (DSA) are rivest-shamir-adleman (RSA) and elliptic curve cryptosystems (ECC) which based on the presumed difficulty of factoring large integers and the algebraic structure of elliptic curves over finite fields. Usually, RSA is computed over GF( p), and ECC is computed over GF( p) or GF(2 p ). Moreover, embedded applications need advance encryption standard (AES) algorithms to process encryption and decryption procedures. In order to reuse the hardware resources and meet the trade-off between area and performance, we proposed a new triple functional arithmetic unit for computing high radix RSA and ECC operations over GF( p) and GF(2 p ), which also can be extended to support AES operations. A new high radix signed digital (SD) adder has been proposed to eliminate the carry propagations over GF( p). The proposed unified design took up 28.7% less hardware resources than implementing RSA, ECC, and AES individually, and the experimental results show that our Received June 1, 2012; accepted December 5, 2012 E-mail: estelle.ywang@gmail.com proposed architecture can achieve 141.8MHz using approximately 5.5k CLBs on Virtex-5 FPGA.