A low power 12-bit 30 MSPS CMOS pipeline ADC with on-chip voltage reference buffer

A 12-bit 30 MSPS pipeline analog-to-digital converter (ADC) implemented in 0.13- mu m 1P8M CMOS technology is presented. Low power design with the front-end sample-and-hold amplifier removed is proposed. Except for the first stage, two-stage cascode-compensated operational amplifiers with dual input...

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Bibliographic Details
Published inJournal of semiconductors Vol. 32; no. 1; pp. 015003 - 1-7
Main Authors Chen, Qihui (奇辉 陈), Qin, Yajie (亚杰 秦), Lu, Bo (波陆), Hong, Zhiliang (志良 洪)
Format Journal Article
LanguageEnglish
Published IOP Publishing 01.01.2011
Subjects
CMOS
Electric potential
Noise levels
Pipelines
Power consumption
Sampling
Semiconductors
Voltage
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ISSN1674-4926
DOI10.1088/1674-4926/32/1/015003

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Summary:A 12-bit 30 MSPS pipeline analog-to-digital converter (ADC) implemented in 0.13- mu m 1P8M CMOS technology is presented. Low power design with the front-end sample-and-hold amplifier removed is proposed. Except for the first stage, two-stage cascode-compensated operational amplifiers with dual inputs are shared between successive stages to further reduce power consumption. The ADC presents 65.3 dB SNR, 75.8 dB SFDR and 64.6 dB SNDR at 5 MHz analog input with 30.7 MHz sampling rate. The chip dissipates 33.6 mW from 1.2 V power supply. FOM is 0.79 pJ/conv step.
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ISSN:1674-4926
DOI:10.1088/1674-4926/32/1/015003