Linear array implementation of the EM algorithm for PET image reconstruction

• Published in: IEEE transactions on nuclear science Vol. 42; no. 4; pp. 1439 - 1444
• Main Authors: Rajan, K., Patnaik, L.M., Ramakrishna, J.
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.08.1995; Institute of Electrical and Electronics Engineers
• Subjects: Biological and medical sciences; Concurrent computing; Convolution; Digital signal processing chips; Image reconstruction; Image storage; Investigative techniques, diagnostic techniques (general aspects); Medical sciences; Miscellaneous. Technology; Positron emission tomography; Radionuclide investigations; Reduced instruction set computing; Signal processing algorithms; Topology; Workstations; Radionuclide study; Array; Function maximization; Algorithm; Implementation; Image reconstruction; Positron; Emission tomography
• ISSN: 0018-9499; 1558-1578
• DOI: 10.1109/23.467723

The PET image reconstruction based on the EM algorithm has several attractive advantages over the conventional convolution backprojection algorithms. However, the PET image reconstruction based on the EM algorithm is computationally burdensome for today's single processor systems. In addition, a large memory is required for the storage of the image, projection data, and the probability matrix. Since the computations are easily divided into tasks executable in parallel, multiprocessor configurations are the ideal choice for fast execution of the EM algorithms. In this study, we attempt to overcome these two problems by parallelizing the EM algorithm on a multiprocessor system. The parallel EM algorithm on a linear array topology using the commercially available fast floating point digital signal processor (DSP) chips as the processing elements (PE's) has been implemented. The performance of the EM algorithm on a 386/387 machine, IBM 6000 RISC workstation, and on the linear array system is discussed and compared. The results show that the computational speed performance of a linear array using 8 DSP chips as PE's executing the EM image reconstruction algorithm is about 15.5 times better than that of the IBM 6000 RISC workstation. The novelty of the scheme is its simplicity. The linear array topology is expandable with a larger number of PE's. The architecture is not dependent on the DSP chip chosen, and the substitution of the latest DSP chip is straightforward and could yield better speed performance.< >