FPGA implementation of hardware efficient adaptive filter robust to impulsive noise

• Published in: Chronic diseases and translational medicine Vol. 11; no. 3; pp. 107 - 116
• Main Authors: Parmar, Chintan A, Ramanadham, Bhaskar, Darji, Anand D
• Format: Journal Article
• Language: English
• Published: Beijing The Institution of Engineering and Technology 01.05.2017; John Wiley & Sons, Inc
• Subjects: Adaptation; adaptive filters; Algorithms; convergence; convergence rate; Digital signal processors; Field programmable gate arrays; field‐programmable gate array; FPGA; hardware description languages; hardware efficient adaptive filter; impulse noise; impulsive noise; Matlab; modified robust mixed norm filter; MRMN adaptive filter algorithm; Research Article; Signal processing; SSE; steady state error; VHDL; Xilinx system generator high level synthesis tool; modified robust mixed norm filter; MRMN adaptive filter algorithm; adaptive filters; field programmable gate arrays; SSE; convergence; FPGA; hardware description languages; Xilinx system generator high level synthesis tool; field-programmable gate array; steady state error; hardware efficient adaptive filter; VHDL; impulse noise; impulsive noise; convergence rate; Matlab
• ISSN: 1751-8601; 1751-861X; 2095-882X; 1751-861X; 2589-0514
• DOI: 10.1049/iet-cdt.2016.0067

Adaptive filters are prevalent in many real-time signal processing applications. Many adaptive algorithms already exist, but most of them assume white Gaussian noise as disturbance. However, for many applications such as electrocardiogram, foetus heart rate measurement, low frequency atmospheric noise, underwater acoustic noise and signal measurement in instrumentation, the impulsive noise is more common. This study presents a modified robust mixed norm (MRMN) adaptive filter algorithm robust to impulsive noise with higher convergence rate and lower steady state error (SSE). MRMN adaptive filter algorithm has been simulated using Matlab and Xilinx system generator high level synthesis tool and a significant improvement in SSE and convergence speed is obtained compared with the existing adaptive filter algorithms for similar specifications. The proposed algorithm is also described using VHDL and synthesised using Xilinx synthesiser tool in order to implement on field-programmable gate array (FPGA). The FPGA post route and place implementation results show nearly 90% reduction in resource utilisation and nearly 2.6 times improvement in clock frequency as compared with the existing FPGA based implementation for similar specifications.