Architectural Exploration to Enable Sufficient MTJ Device Write Margin for STT-RAM Based Cache

• Published in: IEEE transactions on magnetics Vol. 48; no. 8; pp. 2346 - 2351
• Main Authors: Sun, Hongbin, Liu, Chuanyin, Min, Tai, Zheng, Nanning, Zhang, Tong
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.08.2012; Institute of Electrical and Electronics Engineers
• Subjects: Cache memory; Cache storage; Computer architecture; Cross-disciplinary physics: materials science; rheology; Error analysis; error correction code; Error correction codes; Exact sciences and technology; Fault tolerance; Fault tolerant systems; Magnetic tunneling; Materials science; Other topics in materials science; Physics; STT-RAM; write margin; write margin; error correction code; fault tolerance; Cache memory; STT-RAM; Magnetic properties
• ISSN: 0018-9464; 1941-0069
• DOI: 10.1109/TMAG.2012.2193589

As a promising nonvolatile memory technology, magnetic tunnel junction (MTJ) based spin-torque transfer RAM (STT-RAM) has recently attracted much attention. However, recent device research suggested that, in order to maintain sufficient MTJ write margin to prevent device breakdown, MTJs may be subject to unconventionally high random write error rates (e.g., 10 -3 and above) as memory cell size is being scaled down. In this paper, we aim to develop a STT-RAM cache design solutions that can effectively tolerate high MTJ write error rates at small performance and implementation cost, which makes it much easier to maintain sufficient MTJ write margin and hence push the STT-RAM scalability envelope. Using the full system simulator PTLsim and a variety of benchmarks, we show that the proposed architecture design can readily accommodate MTJ write error rate upto 2% at the penalty of less than 3% processor performance degradation, less than 10% silicon area overhead, and negligible energy consumption overhead.