Area-Efficient Nano-AES Implementation for Internet-of-Things Devices

• Published in: IEEE transactions on very large scale integration (VLSI) systems Vol. 29; no. 1; pp. 136 - 148
• Main Authors: Shahbazi, Karim, Ko, Seok-Bum
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.01.2021; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Advanced encryption standard (AES) algorithm; Algorithms; Application specific integrated circuits; Circuit design; clock gating; Clocks; Computer architecture; Cryptography; Design optimization; Devices; Encryption; Field programmable gate arrays; hardware implementation; Integrated circuits; Internet of Things; Internet of Things (IoT); lightweight cryptography; Power consumption; Power demand; Registers
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2020.3033928

Due to the fast-growing number of connected tiny devices to the Internet of Things (IoT), providing end-to-end security is vital. Therefore, it is essential to design the cryptosystem based on the requirement of resource-constrained IoT devices. This article presents a lightweight advanced encryption standard (AES), a high-secure symmetric cryptography algorithm, implementation on field-programmable gate array (FPGA) and 65-nm technology for resource-constrained IoT devices. The proposed architecture includes 8-bit datapath and five main blocks. We design two specified register banks, Key-Register and State-Register, for storing the plain text, keys, and intermediate data. To reduce the area, Shift-Rows is embedded inside the State-Register. To adapt the Mix-Column to 8-bit datapath, we design an optimized 8-bit block for Mix-Columns with four internal registers, which accept 8-bit and send back 8-bit. Also, a shared optimized Sub-Bytes is employed for the key expansion phase and encryption phase. To optimize Sub-Bytes, we merge and simplify some parts of the Sub-Bytes. To reduce power consumption, we apply the clock gating technique to the design. Application-specific integrated circuit (ASIC) implementation results show a respective improvement in the area over the previous similar works from 35% to 2.4%. Based on the results, the proposed design is a suitable cryptosystem for tiny IoT devices.