Reconfigurable Architecture for Noise Cancellation in Acoustic Environment Using Single Multiply Accumulate Adaline Filter

• Published in: Electronics (Basel) Vol. 12; no. 4; p. 810
• Main Authors: Ezilarasan, M. R., Britto Pari, J., Leung, Man-Fai
• Format: Journal Article
• Language: English
• Published: Basel MDPI AG 01.02.2023
• Subjects: Acoustic noise; Adaptive algorithms; Adaptive filters; Artificial neural networks; Bias; Complexity; Computer architecture; Delay lines; Digital integrated circuits; Electric filters; Field programmable gate arrays; FIR filters; Hardware description languages; Mean square errors; Neural networks; Optimization; Signal processing; India
• ISSN: 2079-9292; 2079-9292
• DOI: 10.3390/electronics12040810

The creation of multiple applications with a higher level of complexity has been made possible by the usage of artificial neural networks (ANNs). In this research, an efficient flexible finite impulse response (FIR) filter structure called ADALINE (adaptive linear element) that makes use of a MAC (multiply accumulate) core is proposed. The least mean square (LMS) and recursive least square (RLS) algorithms are the most often used methods for maximizing filter coefficients. Despite outperforming the LMS, the RLS approach has not been favored for real-time applications due to its higher design arithmetic complexity. To achieve less computation, the fundamental filter has utilized an LMS-based tapping delay line filter, which is practically a workable option for an adaptive filtering algorithm. To discover the undiscovered system, the adjustable coefficient filters have been developed in the suggested work utilizing an optimal LMS approach. The 10-tap filter being considered here has been analyzed and synthesized utilizing field programmable gate array (FPGA) devices and programming in hardware description language. In terms of how well the resources were used, the placement and postrouting design performed well. If the implemented filter architecture is compared with the existing filter architecture, it reveals a 25% decrease in resources from the existing one and an increase in clock frequency of roughly 20%.