A 150-MS/s Fully Dynamic SAR-Assisted Pipeline ADC Using a Floating Ring Amplifier and Gain-Enhancing Miller Negative-C

• Published in: IEEE open journal of solid-state circuits Vol. 5; pp. 145 - 156
• Main Authors: Song, Seungheun, Kang, Taewook, Lee, Seungjong, Flynn, Michael P.
• Format: Journal Article
• Language: English
• Published: New York IEEE 2025; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Analog to digital converters; Analog-to-digital converter (ADC); Capacitance; Capacitors; Circuits; Closed loops; Error compensation; Error correction; Feedback; Feedback circuits; Flora; Gain; gain enhancement; gain error correction; Inverters; Miller negative capacitance (Miller negative-C); MOS devices; multiplying digital-to-analog converter (MDAC); negative capacitance (negative-C); Operational amplifiers; pipelined SAR ADC; Pipelines; Power consumption; Power demand; Reservoirs; residue amplifier; ring amplifier; SAR-assisted pipeline ADC
• ISSN: 2644-1349; 2644-1349
• DOI: 10.1109/OJSSCS.2024.3513255

This article introduces a fully dynamic SAR-assisted pipeline analog-to-digital converter (ADC) that uses a floating ring amplifier (FLORA) and gain-enhancing Miller negative capacitance (Miller negative-C). FLORA is a fully dynamic and bias-free ring amplifier powered by reservoir capacitors. Different reservoir capacitors for auto-zero and amplification phases optimize the power consumption and dominant pole locations. Furthermore, FLORA enhances speed without needing common-mode load capacitors in each stage and does not need a switched-capacitor common-mode feedback circuit at the output. The Miller negative-C improves the accuracy of the closed-loop residue amplifier by reducing the gain error related to the product of the finite operational amplifier gain and the feedback factor. This gain error compensation scheme eliminates the need for extra circuitry or correction phases. It occupies a small area and requires little additional power consumption. This article analyzes the stability, effective range, and settling behavior of an amplifier with Miller negative-C. The prototype ADC implemented in a 28-nm CMOS process achieves an SNDR and an SFDR of 67.9 and 84.3 dB, respectively, while consuming 1.72 mW at 150 MS/s from a 1-V supply. The corresponding Walden and Schreier SNDR figure of merits are 5.7 fJ/conversion-step and 173 dB, respectively.