A 0.31-1 GHz Fast-Corrected Duty-Cycle Corrector With Successive Approximation Register for DDR DRAM Applications

• Published in: IEEE transactions on very large scale integration (VLSI) systems Vol. 20; no. 8; pp. 1524 - 1528
• Main Authors: MIN, Young-Jae, JEONG, Chan-Hui, KIM, Kyu-Young, WON HO CHOI, SON, Jong-Pil, KIM, Chulwoo, KIM, Soo-Won
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.08.2012; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Applied sciences; Approximation; Circuits; Clocks; CMOS; Delay lines; Design. Technologies. Operation analysis. Testing; Detectors; Double data rate (DDR); DRAM; duty-cycle corrector (DCC); Electronics; Error analysis; Errors; Exact sciences and technology; General equipment and techniques; Generators; Instruments, apparatus, components and techniques common to several branches of physics and astronomy; Integrated circuits; Integrated circuits by function (including memories and processors); Mathematical analysis; Physics; Random access memory; Registers; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Sensors (chemical, optical, electrical, movement, gas, etc.); remote sensing; Solid state circuits; successive approximation register (SAR) controller; Very large scale integration; Double data rate (DDR); Die; duty-cycle corrector (DCC); Random access memory; Control system; Measurement sensor; Output circuit; Output signal; Implementation; Search algorithm; Register file; Successive approximation; successive approximation register (SAR) controller; Non volatile memory; Complementary MOS technology; Integrated circuit; DRAM; Separator circuit; Dynamic random access memory
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2011.2158011

This brief presents a duty cycle corrector (DCC) using a binary search algorithm with successive approximation register (SAR). The proposed DCC consists of a duty-cycle detector, a duty-cycle adjuster, its controller and an output buffer. In order to achieve fast duty-correction with a small die area, a SAR-controller is exploited as a duty-correction controller. The proposed DCC circuit has been implemented and fabricated in a 0.13-μm CMOS process and occupies 0.048 mm 2 . The measured duty-cycle error for the 50% duty-rate is below 1% (or 10 pS) within 320 pS external input duty-cycle error. The duty of output signal is corrected only with 14 cycles. This DCC operates from 312.5 MHz to 1 GHz and dissipates 3.2 mW at 1 GHz.