CMOS 120 GHz Phase-Locked Loops Based on Two Different VCO Topologies

• Published in: Journal of Electromagnetic Engineering and Science Vol. 17; no. 2; pp. 98 - 104
• Main Authors: Junghwan Yoo, Jae-Sung Rieh
• Format: Journal Article
• Language: English
• Published: 한국전자파학회JEES 01.04.2017; 한국전자파학회
• Subjects: 전자/정보통신공학; Voltage-Controlled Oscillator (VCO); CMOS; Phase-Locked Loop (PLL); Frequency Doubler; Signal Source
• ISSN: 2671-7255; 2671-7263
• DOI: 10.5515/JKIEES.2017.17.2.98

This work describes the development and comparison of two phase-locked loops (PLLs) based on a 65-nm CMOS technology. The PLLs incorporate two different topologies for the output voltage-controlled oscillator (VCO): LC cross-coupled and differential Colpitts. The measured locking ranges of the LC cross-coupled VCO-based phase-locked loop (PLL1) and the Colpitts VCO-based phase-locked loop (PLL2) are 119.84−122.61 GHz and 126.53−129.29 GHz, respectively. Th e output powers of PLL1 and PLL2 are −8.6 dBm and −10.5 dBm with DC power consumptions of 127.3 mW and 142.8 mW, respectively. The measured phase noise of PLL1 is −59.2 at 10 kHz offset and −104.5 at 10 MHz offset, and the phase noise of PLL2 is −60.9 dBc/Hz at 10 kHz offset and −104.4 dBc/Hz at 10 MHz offset. The chip sizes are 1,080 μm × 760 μm (PLL1) and 1,100 μm × 800 μm (PLL2), including the probing pads. KCI Citation Count: 1