A Novel Architecture for Block Interleaving Algorithm in MB-OFDM Using Mixed Radix System

• Published in: IEEE transactions on very large scale integration (VLSI) systems Vol. 18; no. 6; pp. 1020 - 1024
• Main Authors: Youngsun Han, Harliman, Peter, Seon Wook Kim, Jong-Kook Kim, Chulwoo Kim
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.06.2010; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Applied sciences; Architecture; Array processor; block interleaving; Blocking; Clocks; Communication standards; Complexity; Delay; Design engineering; Design methodology; Design. Technologies. Operation analysis. Testing; Electronics; Energy consumption; Exact sciences and technology; Frequency; Integrated circuits; Integrated circuits by function (including memories and processors); Interleaved codes; MB-OFDM; Mixed Radix System (MRS); Permutations; Power consumption; Research and development; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Standards development; Throughput; Very large scale integration; Array processor; Modular design; Permutation; MB-OFDM; Clock; Algorithm; block interleaving; Implementation; Operating rate; Mixed Radix System (MRS); Integrated circuit; Electric power consumption; Orthogonal frequency division multiplexing
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2009.2018091

In this paper, we present a novel architecture of a block interleaver in MB-OFDM systems based on Mixed Radix System (MRS). We prove mathematically that the proposed architecture can support bit permutations in the interleaving process. The hierarchical property of our proposed MRS-based design methodology allows the proposed architecture to support all the required data rates in the MB-OFDM systems with simple modular design. Furthermore, the same design to be used for the interleaver can also be used for the operation of de-interleaving, which reduces the implementation complexity significantly. The latency of our architecture is as low as 6 MB-OFDM symbols. In addition, when comparing our proposed architecture with the conventional approach, we are able to reduce the implementation complexity by 85.5%, 69.4%, and 40.3% for 80, 200, and 480 Mb/s data rates, respectively, while improving our operating maximum clock frequency by more than 3.3 times over the conventional design. We also show that the power consumption is reduced by 87.4%, 73.6%, and 39.8% for 80, 200, and 480 Mb/s, respectively.