Addressing DC Component in PLL and Notch Filter Algorithms

• Published in: IEEE transactions on power electronics Vol. 27; no. 1; pp. 78 - 86
• Main Authors: Karimi-Ghartemani, M., Khajehoddin, S. A., Jain, P. K., Bakhshai, A., Mojiri, M.
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.01.2012; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Adaptive notch filter (ANF); Algorithms; Applied sciences; Capacitors. Resistors. Filters; Circuit properties; Circuits of signal characteristics conditioning (including delay circuits); dc component; dc offset; Direct current; Dynamical systems; Dynamics; Electric currents; Electric, optical and optoelectronic circuits; Electrical engineering. Electrical power engineering; Electrical equipment; Electronic circuits; Electronics; enhanced phase-locked loop (EPLL); Estimation; Exact sciences and technology; Filtering; Filtration; Frequencies; Frequency estimation; Frequency filters; Frequency locked loops; Harmonic analysis; notch filter (NF); Notch filters; orthogonal signal generator (OSG); Oscillators, resonators, synthetizers; Phase locked loops; phase-locked loop (PLL); Power system dynamics; second-order generalized integrator frequency-locked loop (SOGI-FLL); Simulation; Synchronization; synchronous reference-frame phase-locked loop (SRF-PLL); Various equipment and components; Second order; Input signal; orthogonal signal generator (OSG); Low frequency; Offset voltage; Addressing; dc component; Notch filter; Adaptive notch filter (ANF); second-order generalized integrator frequency-locked loop (SOGI-FLL); Oscillation; Integrator; dc offset; Dynamic response; Dynamic characteristic; System design; Adaptive filter; Experimental study; Synchronization; Algorithm; phase-locked loop (PLL); Phase locked loop; synchronous reference-frame phase-locked loop (SRF-PLL); Three phase circuit; Signal generators; System simulation; enhanced phase-locked loop (EPLL); Frequency filtering; High frequency; notch filter (NF)
• ISSN: 0885-8993; 1941-0107
• DOI: 10.1109/TPEL.2011.2158238

This paper presents a method for addressing the dc component in the input signal of the phase-locked loop (PLL) and notch filter algorithms applied to filtering and synchronization applications. The dc component may be intrinsically present in the input signal or may be generated due to temporary system faults or due to the structure and limitations of the measurement/conversion processes. Such a component creates low-frequency oscillations in the loop that cannot be removed using filters because such filters will significantly degrade the dynamic response of the system. The proposed method is based on adding a new loop inside the PLL structure. It is structurally simple and, unlike an existing method discussed in this paper, does not compromise the high-frequency filtering level of the concerned algorithm. The method is formulated for three-phase and single-phase systems, its design aspects are discussed, and simulations/experimental results are presented.