Characterisation and modeling of mismatch in MOS transistors for precision analog design

• Published in: IEEE journal of solid-state circuits Vol. 21; no. 6; pp. 1057 - 1066
• Main Authors: Lakshmikumar, K.R., Hadaway, R.A., Copeland, M.A.
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.12.1986; Institute of Electrical and Electronics Engineers
• Subjects: Analog circuits; Analytical models; Applied sciences; Circuit properties; CMOS process; Current measurement; Digital-analog conversion; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Exact sciences and technology; MOS capacitors; MOSFETs; Semiconductor device modeling; Switched capacitor circuits; Telecommunications; Analog circuit; MOS technology; Transistor; Models; Circuit matching; Circuit design
• ISSN: 0018-9200
• DOI: 10.1109/JSSC.1986.1052648

A characterization methodology is presented that accurately predicts the mismatch in drain current over a wide operating range using a minimum set of measured data. The physical causes of mismatch are discussed in detail for both p- and n-channel devices. Statistical methods are used to develop analytical models that relate the mismatch to the device dimensions. It is shown that these models are valid for small-geometry devices only. Extensive experimental data from a 3-/spl mu/m CMOS process are used to verify the models. The application of the transistor matching studies to the design of a high-performance digital-to-analog converter (DAC) is discussed. A circuit design methodology is presented that highlights the close interaction between the circuit yield and the matching accuracy of devices. It has been possible to achieve a circuit yield of greater than 97% as a result of the knowledge generated regarding the matching behavior of transistors and due to the systematic design approach.