Digit-pipelined direct digital frequency synthesis based on differential CORDIC

• Published in: IEEE transactions on circuits and systems. I, Regular papers Vol. 53; no. 5; pp. 1035 - 1044
• Main Authors: Chang Yong Kang, Swartzlander, E.E.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.05.2006; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Accumulators; Algorithms; Architecture; Circuits; Computer architecture; differential CORDIC (DCORDIC); Digit-level pipelining; Digital; Digital arithmetic; direct digital frequency synthesis (DDFS); Frequency synthesizers; Hardware design languages; Iterative algorithms; on-line arithmetic; Oscillators; Pipeline processing; Pipelining (computers); Read only memory; Synthesis; systolic array; Systolic arrays; Tuning; Two dimensional
• ISSN: 1549-8328; 1558-0806
• DOI: 10.1109/TCSI.2005.862183

A novel direct digital frequency synthesis (DDFS) architecture based on the differential CORDIC (DCORDIC) algorithm is presented. The architecture allows digit-level pipelining in the CORDIC angle path by implementing a two-dimensional systolic array. Unlike other DDFS architectures, it incorporates the phase accumulator in the digit-level pipelining framework so that a bottleneck-free datapath throughout the whole system is achieved in a scalable manner. A generic environment that generates fully synthesizable Verilog codes that implement the proposed architecture is created and the physical attributes of the resulting system are discussed.