Reconfigurable 2, 3 and 5-point DFT processing element for SDF FFT architecture using fast cyclic convolution algorithm

• Published in: Electronics letters Vol. 56; no. 12; pp. 592 - 594
• Main Authors: S, Bibin Sam Paul, Glittas, A.X, Sellathurai, M, Lakshminarayanan, G
• Format: Journal Article
• Language: English
• Published: The Institution of Engineering and Technology 11.06.2020
• Subjects: 2‐point DFT processing element; 3‐point DFT structures; 5‐input PE; 5‐point DFT computation operation; 5‐point PE designs; adder; adders; Circuits and systems; convolution; cyclic convolution units; discrete Fourier transforms; fast cyclic convolution algorithm; fast Fourier transforms; logic design; multiplexers; multiplier; multiplying circuits; PE architecture; pipeline arithmetic; pipelined SDF FFT architecture; reconfigurable architectures; reconfigurable processing element; fast Fourier transforms; reconfigurable processing element; multiplying circuits; discrete Fourier transforms; 5-point PE designs; multiplier; 5-input PE; pipeline arithmetic; adder; 3-point DFT structures; pipelined SDF FFT architecture; cyclic convolution units; fast cyclic convolution algorithm; 5-point DFT computation operation; multiplexers; adders; reconfigurable architectures; convolution; 2-point DFT processing element; PE architecture; logic design
• ISSN: 0013-5194; 1350-911X; 1350-911X
• DOI: 10.1049/el.2019.4262

In this Letter, a reconfigurable processing element (PE) for pipelined SDF FFT architecture is presented, which can be configured to compute 2, 3 and 5-point DFTs. Foremost, the proposed PE architecture for the 5-point DFT computation is designed by factorising the 5-point DFT computation operation into $2\times 2$2×2 cyclic convolution units and then the 2- and 3-point DFTs structures are mapped on to it using multiplexers. Thus, all three configurations are possible. In the case of prior 5-point PE designs, the PE can start its operation only after the arrival of all the five-input data, whereas the proposed PE completes a part of computation after the arrival of the first three inputs and reuse the same hardware to process the next two inputs. As a result, the proposed PE requires less hardware, at the same time, preserving the throughput of prior PE. The proposed PE required 25% less multiplier and one adder less compared to the Winograd algorithm based 5-input PE.