Methods for true energy-performance optimization

• Published in: IEEE journal of solid-state circuits Vol. 39; no. 8; pp. 1282 - 1293
• Main Authors: Markovic, D., Stojanovic, V., Nikolic, B., Horowitz, M.A., Brodersen, R.W.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.08.2004; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Circuit optimization; Circuit topology; Circuits; Constraint optimization; Cost engineering; Degrees of freedom; Delay; Delay effects; Design optimization; Energy conservation; Energy efficiency; Equalization; Leakage current; Mathematical analysis; Optimization; Optimization methods; Parallel processing; Threshold voltage
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2004.831796

This paper presents methods for efficient energy-performance optimization at the circuit and micro-architectural levels. The optimal balance between energy and performance is achieved when the sensitivity of energy to a change in performance is equal for all the design variables. The sensitivity-based optimizations minimize energy subject to a delay constraint. Energy savings of about 65% can be achieved without delay penalty with equalization of sensitivities to sizing, supply, and threshold voltage in a 64-bit adder, compared to the reference design sized for minimum delay. Circuit optimization is effective only in the region of about /spl plusmn/30% around the reference delay; outside of this region the optimization becomes too costly either in terms of energy or delay. Using optimal energy-delay tradeoffs from the circuit level and introducing more degrees of freedom, the optimization is hierarchically extended to higher abstraction layers. We focus on the micro-architectural optimization and demonstrate that the scope of energy-efficient optimization can be extended by the choice of circuit topology or the level of parallelism. In a 64-bit ALU example, parallelism of five provides a three-fold performance increase, while requiring the same energy as the reference design. Parallel or time-multiplexed solutions significantly affect the area of their respective designs, so the overall design cost is minimized when optimal energy-area tradeoff is achieved.