A decoupling technique for efficient timing analysis of VLSI interconnects with dynamic circuit switching

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems Vol. 23; no. 9; pp. 1321 - 1337
• Main Authors: Yungseon Eo, Seongkyun Shin, Eisenstadt, W.R., Jongin Shim
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.09.2004; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Circuit synthesis; Circuits; Computer errors; Coupling circuits; Delay; Design engineering; Dynamics; Integrated circuit interconnections; Integrated circuits; Mathematical models; Pattern analysis; RLC circuits; Switching; Switching circuits; Time measurements; Timing; Very large scale integration
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/TCAD.2004.831571

In today's high-speed/high-density very large scale integrated (VLSI) circuit designs with coupled interconnect lines, signal transients are strongly correlated with the input switching patterns. Signal-delay variations due to the input-switching patterns may be more than /spl plusmn/50% of the delay of an isolated single line. Thus, blind static timing-analysis techniques without consideration of the detailed switching effects may not be accurate enough to meet tight timing margins for today's deep submicron (DSM)-based VLSI circuits. In this paper, the signal-transient responses of multicoupled interconnect lines due to various input-switching patterns are analyzed in terms of the effective capacitances and effective inductances. Thereby, the critical delay line of multicoupled interconnect lines is decoupled into an effective single-isolated line. With the proposed novel decoupling technique for multicoupled interconnect lines, the accurate dynamic delay of strongly coupled interconnect lines can be readily determined with physical layout information. For example, in switching patterns, the paper shows that the signal delays calculated by using the effective single-line models have excellent agreement with SPICE simulations using the generic coupled interconnect circuit models. That is, the accuracy for both RC-dominant lines and RLC lines is within 10% error (but often within 5% error). Thus, without any significant modification of existing IC computer-aided design frameworks, the technique can be directly as well as usefully employed for accurate timing verification of DSM-based VLSI designs.