Area-Optimal Transistor Folding for 1-D Gridded Cell Design

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems Vol. 32; no. 11; pp. 1708 - 1721
• Main Author: Cortadella, Jordi
• Format: Journal Article Publication
• Language: English
• Published: IEEE 01.11.2013
• Subjects: Algorithm design and analysis; Cell generation; Components electrònics; Design for manufacturability; Enginyeria electrònica; Integrated circuit modeling; Layout; Legged locomotion; Linear programming; Logic gates; Strips; Transistor folding; Transistor sizing; Transistors; Àrees temàtiques de la UPC
• ISSN: 0278-0070; 1937-4151; 1937-4151
• DOI: 10.1109/TCAD.2013.2269680

The 1-D design style with gridded design rules is gaining ground for addressing the printability issues in subwavelength photolithography. One of the synthesis problems in cell generation is transistor folding, which consists of breaking large transistors into smaller ones (legs) that can be placed in the active area of the cell. In the 1-D style, diffusion sharing between differently sized transistors is not allowed, thus implying a significant area overhead when active areas with different sizes are required. This paper presents a new formulation of the transistor folding problem in the context of 1-D design style and a mathematical model that delivers area-optimal solutions. The mathematical model can be customized for different variants of the problem, considering flexible transistor sizes and multiple-height cells. An innovative feature of the method is that area optimality can be guaranteed without calculating the actual location of the transistors. The model can also be enhanced to deliver solutions with good routability properties.