Design of Reference-free Flash ADC With On-chip Rank-based Comparator Selection Using Multiple Comparator Groups
Statistical element selection has been proposed to solve the offset voltage variation problem for a flash ADC. A calibration method based on order statistics has been proposed for statistical selection that does not require offset voltage measurement. This paper presents a design methodology of flas...
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| Published in | IPSJ Transactions on System and LSI Design Methodology Vol. 17; pp. 36 - 43 |
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| Main Authors | , , , |
| Format | Journal Article |
| Language | English |
| Published |
Tokyo
Information Processing Society of Japan
01.01.2024
Japan Science and Technology Agency |
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| Online Access | Get full text |
| ISSN | 1882-6687 1882-6687 |
| DOI | 10.2197/ipsjtsldm.17.36 |
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| Abstract | Statistical element selection has been proposed to solve the offset voltage variation problem for a flash ADC. A calibration method based on order statistics has been proposed for statistical selection that does not require offset voltage measurement. This paper presents a design methodology of flash ADC with such calibration using multiple comparator groups. We validate our proposal with measurement results from test chips fabricated in a commercial 65nm general-purpose process. Measurement results confirm that rank-based comparator selection achieves a reference-free ADC. Compared to the baseline ADC, where only one group of comparators is used, the ADC with three groups significantly increases the linearity and input range under the same power consumption. As no reference voltage and DACs are required, the proposed ADC design will help realize ADCs in advanced process nodes with lower power consumption. |
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| AbstractList | Statistical element selection has been proposed to solve the offset voltage variation problem for a flash ADC. A calibration method based on order statistics has been proposed for statistical selection that does not require offset voltage measurement. This paper presents a design methodology of flash ADC with such calibration using multiple comparator groups. We validate our proposal with measurement results from test chips fabricated in a commercial 65nm general-purpose process. Measurement results confirm that rank-based comparator selection achieves a reference-free ADC. Compared to the baseline ADC, where only one group of comparators is used, the ADC with three groups significantly increases the linearity and input range under the same power consumption. As no reference voltage and DACs are required, the proposed ADC design will help realize ADCs in advanced process nodes with lower power consumption. |
| Author | Wada, Osami Islam, Mahfuzul Hisakado, Takashi Kitamura, Takehiro |
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| References | [2] Fahmy, A., Liu, J., Kim, T. and Maghari, N.: An all-digital scalable and reconfigurable wide-input range stochastic ADC using only standard cells, IEEE Trans. Circuits Syst. II: Express Briefs, Vol.62, No.8, pp.731-735 (2015). [9] Kitamura, T., Islam, M., Hisakado, T. and Wada, O.: Flash ADC utilizing offset voltage variation with order statistics based comparator selection, Proc. Int. Symp. Qual. Electron. Des. ISQED, pp.103-108 (2021). [17] Razavi, B.: The design of a comparator [the analog mind], IEEE Solid-State Circuits Mag., Vol.12, No.4, pp.8-14 (2020). [11] Hossain, M.M., Iizuka, T., Nakura, T. and Asada, K.: Optimal design method of sub-ranging ADC based on stochastic comparator, IEICE Trans. Fundam. Electron. Commun. Comput. Sci., Vol.E101-A, No.2, pp.410-424 (2018). [12] Asano, T., Hirai, Y., Tani, S., Yano, S., Jo, I. and Matsuoka, T.: An offset distribution modification technique of stochastic flash ADC, IEICE Electron. Express, Vol.13, No.6, pp.20160115-20160115 (2016). [3] Jeon, M.K., Yoo, W.J., Kim, C.G. and Yoo, C.: A stochastic flash analog-to-digital converter linearized by reference swapping, IEEE Access, Vol.5, pp.23046-23051 (2017). [7] Chen, V.H. and Pileggi, L.: An 8.5mW 5GS/s 6b flash ADC with dynamic offset calibration in 32nm CMOS SOI, IEEE Symposium on VLSI Circuits, pp.264-265 (2013). [14] Kitamura, T., Islam, M., Hisakado, T. and Wada, O.: Performance improvement of order statistics based flash ADC using multiple comparator groups, IEEE Interregional NEWCAS Conference (NEWCAS), pp.1-4 (2022). [5] Van der Plas, G., Decoutere, S. and Donnay, S.: A 0.16pJ/conversion-step 2.5mW 1.25GS/s 4b ADC in a 90nm digital CMOS process, IEEE Int. Solid-State Circuits Conf., pp.566-567 (2006). [8] Shu, Y.S.: A 6b 3GS/s 11mW fully dynamic flash ADC in 40nm CMOS with reduced number of comparators, Symposium on VLSI Circuits (VLSIC), pp.26-27 (2012). [13] Sugimoto, T., Tanimoto, H. and Yoshizawa, S.: Estimation of number of comparators required in n-bit stochastic flash AD converters, Electron. Commun. Jpn., Vol.99, No.6, pp.22-30 (2016). [1] Weaver, S., Hershberg, B., Kurahashi, P., Knierim, D. and Moon, U.K.: Stochastic flash analog-to-digital conversion, IEEE Trans. Circuits Syst. I: Regul. Pap., Vol.57, No.11, pp.2825-2833 (2010). [6] Sundstrom, T. and Alvandpour, A.: Utilizing process variations for reference generation in a flash ADC, IEEE Trans. Circuits Syst. II: Express Briefs, Vol.56, No.5, pp.364-368 (2009). [10] Kitamura, T., Islam, M., Hisakado, T. and Wada, O.: Order statistics based low-power flash ADC with on-chip comparator selection, IEICE Trans. Fundam. Electron. Commun. Comput. Sci., Vol.E105-A, No.11, pp.1450-1457 (2022). [15] Tsunomura, T., Nishida, A., Yano, F., Putra, A.T., Takeuchi, K., Inaba, S., Kamohara, S., Terada, K. , Hiramoto, T. and Mogami, T.: Analyses of 5σ Vth fluctuation in 65nm-MOSFETs using Takeuchi plot, IEEE Symposium on VLSI Technology, pp.156-157 (2008). [16] Razavi, B.: The strongARM latch [a circuit for all seasons], IEEE Solid-State Circuits Mag., Vol.7, No.2, pp.12-17 (2015). [4] Uto, S. and Ohhata, K.: Stochastic subranging ADC using variable comparator offset technique, IEEE Int. Symp. Radio-Frequency Integr. Technol. RFIT 2020, No.September, pp.232-234 (2020). 11 12 13 14 15 16 17 1 2 3 4 5 6 7 8 9 10 |
| References_xml | – reference: [16] Razavi, B.: The strongARM latch [a circuit for all seasons], IEEE Solid-State Circuits Mag., Vol.7, No.2, pp.12-17 (2015). – reference: [10] Kitamura, T., Islam, M., Hisakado, T. and Wada, O.: Order statistics based low-power flash ADC with on-chip comparator selection, IEICE Trans. Fundam. Electron. Commun. Comput. Sci., Vol.E105-A, No.11, pp.1450-1457 (2022). – reference: [1] Weaver, S., Hershberg, B., Kurahashi, P., Knierim, D. and Moon, U.K.: Stochastic flash analog-to-digital conversion, IEEE Trans. Circuits Syst. I: Regul. Pap., Vol.57, No.11, pp.2825-2833 (2010). – reference: [4] Uto, S. and Ohhata, K.: Stochastic subranging ADC using variable comparator offset technique, IEEE Int. Symp. Radio-Frequency Integr. Technol. RFIT 2020, No.September, pp.232-234 (2020). – reference: [11] Hossain, M.M., Iizuka, T., Nakura, T. and Asada, K.: Optimal design method of sub-ranging ADC based on stochastic comparator, IEICE Trans. Fundam. Electron. Commun. Comput. Sci., Vol.E101-A, No.2, pp.410-424 (2018). – reference: [2] Fahmy, A., Liu, J., Kim, T. and Maghari, N.: An all-digital scalable and reconfigurable wide-input range stochastic ADC using only standard cells, IEEE Trans. Circuits Syst. II: Express Briefs, Vol.62, No.8, pp.731-735 (2015). – reference: [8] Shu, Y.S.: A 6b 3GS/s 11mW fully dynamic flash ADC in 40nm CMOS with reduced number of comparators, Symposium on VLSI Circuits (VLSIC), pp.26-27 (2012). – reference: [12] Asano, T., Hirai, Y., Tani, S., Yano, S., Jo, I. and Matsuoka, T.: An offset distribution modification technique of stochastic flash ADC, IEICE Electron. Express, Vol.13, No.6, pp.20160115-20160115 (2016). – reference: [9] Kitamura, T., Islam, M., Hisakado, T. and Wada, O.: Flash ADC utilizing offset voltage variation with order statistics based comparator selection, Proc. Int. Symp. Qual. Electron. Des. ISQED, pp.103-108 (2021). – reference: [3] Jeon, M.K., Yoo, W.J., Kim, C.G. and Yoo, C.: A stochastic flash analog-to-digital converter linearized by reference swapping, IEEE Access, Vol.5, pp.23046-23051 (2017). – reference: [7] Chen, V.H. and Pileggi, L.: An 8.5mW 5GS/s 6b flash ADC with dynamic offset calibration in 32nm CMOS SOI, IEEE Symposium on VLSI Circuits, pp.264-265 (2013). – reference: [15] Tsunomura, T., Nishida, A., Yano, F., Putra, A.T., Takeuchi, K., Inaba, S., Kamohara, S., Terada, K. , Hiramoto, T. and Mogami, T.: Analyses of 5σ Vth fluctuation in 65nm-MOSFETs using Takeuchi plot, IEEE Symposium on VLSI Technology, pp.156-157 (2008). – reference: [5] Van der Plas, G., Decoutere, S. and Donnay, S.: A 0.16pJ/conversion-step 2.5mW 1.25GS/s 4b ADC in a 90nm digital CMOS process, IEEE Int. Solid-State Circuits Conf., pp.566-567 (2006). – reference: [6] Sundstrom, T. and Alvandpour, A.: Utilizing process variations for reference generation in a flash ADC, IEEE Trans. Circuits Syst. II: Express Briefs, Vol.56, No.5, pp.364-368 (2009). – reference: [13] Sugimoto, T., Tanimoto, H. and Yoshizawa, S.: Estimation of number of comparators required in n-bit stochastic flash AD converters, Electron. Commun. Jpn., Vol.99, No.6, pp.22-30 (2016). – reference: [14] Kitamura, T., Islam, M., Hisakado, T. and Wada, O.: Performance improvement of order statistics based flash ADC using multiple comparator groups, IEEE Interregional NEWCAS Conference (NEWCAS), pp.1-4 (2022). – reference: [17] Razavi, B.: The design of a comparator [the analog mind], IEEE Solid-State Circuits Mag., Vol.12, No.4, pp.8-14 (2020). – ident: 10 doi: 10.1587/transfun.2021KEP0007 – ident: 3 doi: 10.1109/ACCESS.2017.2766671 – ident: 4 doi: 10.1109/RFIT49453.2020.9226236 – ident: 14 doi: 10.1109/NEWCAS52662.2022.9842172 – ident: 15 – ident: 8 doi: 10.1109/VLSIC.2012.6243772 – ident: 1 doi: 10.1109/TCSI.2010.2050225 – ident: 16 doi: 10.1109/MSSC.2015.2418155 – ident: 5 doi: 10.1109/ISSCC.2006.1696294 – ident: 9 doi: 10.1109/ISQED51717.2021.9424288 – ident: 13 doi: 10.1002/ecj.11817 – ident: 17 doi: 10.1109/MSSC.2020.3021865 – ident: 7 – ident: 11 doi: 10.1587/transfun.E101.A.410 – ident: 12 doi: 10.1587/elex.13.20160115 – ident: 6 doi: 10.1109/TCSII.2009.2019165 – ident: 2 doi: 10.1109/TCSII.2015.2415231 |
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| Snippet | Statistical element selection has been proposed to solve the offset voltage variation problem for a flash ADC. A calibration method based on order statistics... |
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| SubjectTerms | Calibration Comparators distribution tuning Electrical measurement flash ADC Johnson distribution normal distribution offset voltage on-chip calibration order statistics Power consumption |
| Title | Design of Reference-free Flash ADC With On-chip Rank-based Comparator Selection Using Multiple Comparator Groups |
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