Design of Reference-free Flash ADC With On-chip Rank-based Comparator Selection Using Multiple Comparator Groups

• Published in: IPSJ Transactions on System and LSI Design Methodology Vol. 17; pp. 36 - 43
• Main Authors: Kitamura, Takehiro, Wada, Osami, Islam, Mahfuzul, Hisakado, Takashi
• Format: Journal Article
• Language: English
• Published: Tokyo Information Processing Society of Japan 01.01.2024; Japan Science and Technology Agency
• Subjects: Calibration; Comparators; distribution tuning; Electrical measurement; flash ADC; Johnson distribution; normal distribution; offset voltage; on-chip calibration; order statistics; Power consumption
• ISSN: 1882-6687; 1882-6687
• DOI: 10.2197/ipsjtsldm.17.36

Statistical element selection has been proposed to solve the offset voltage variation problem for a flash ADC. A calibration method based on order statistics has been proposed for statistical selection that does not require offset voltage measurement. This paper presents a design methodology of flash ADC with such calibration using multiple comparator groups. We validate our proposal with measurement results from test chips fabricated in a commercial 65nm general-purpose process. Measurement results confirm that rank-based comparator selection achieves a reference-free ADC. Compared to the baseline ADC, where only one group of comparators is used, the ADC with three groups significantly increases the linearity and input range under the same power consumption. As no reference voltage and DACs are required, the proposed ADC design will help realize ADCs in advanced process nodes with lower power consumption.