Multibillion packet lookup for next generation networks
Fast Internet Protocol Version 4 (IPv4) lookup is one of the key challenges that have always been faced with growing internet speed. Next generation networks promise hundreds of gigabit communication bandwidths. To support such high data rates, core networking devices require very fast IPv4 lookup f...
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| Published in | Computers & electrical engineering Vol. 84; pp. 106612 - 11 |
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| Main Authors | , , , , , |
| Format | Journal Article |
| Language | English |
| Published |
Amsterdam
Elsevier Ltd
01.06.2020
Elsevier BV |
| Subjects | |
| Online Access | Get full text |
| ISSN | 0045-7906 1879-0755 |
| DOI | 10.1016/j.compeleceng.2020.106612 |
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| Abstract | Fast Internet Protocol Version 4 (IPv4) lookup is one of the key challenges that have always been faced with growing internet speed. Next generation networks promise hundreds of gigabit communication bandwidths. To support such high data rates, core networking devices require very fast IPv4 lookup for incoming packets to sustain their functionality. Researchers from academia and industry have contributed widely towards this problem, presenting numerous techniques and algorithms to improve lookup times. In this paper, a bit vector-based IP lookup engine is presented that implements parallel units to achieve 4.3 Billion Packets Per Second (BPPS) lookup speeds for 5 fields. Implementations are done using dual port Distributed RAM (DRAM) on state-of-the-art Xilinx Virtex 7 series Field Programmable Gate Arrays (FPGA). Post place and route results for different configurations showed that the proposed design consumes much less memory, facilitating multiple engines on a single chip whilst maintaining a very low overall power profile. |
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| AbstractList | Fast Internet Protocol Version 4 (IPv4) lookup is one of the key challenges that have always been faced with growing internet speed. Next generation networks promise hundreds of gigabit communication bandwidths. To support such high data rates, core networking devices require very fast IPv4 lookup for incoming packets to sustain their functionality. Researchers from academia and industry have contributed widely towards this problem, presenting numerous techniques and algorithms to improve lookup times. In this paper, a bit vector-based IP lookup engine is presented that implements parallel units to achieve 4.3 Billion Packets Per Second (BPPS) lookup speeds for 5 fields. Implementations are done using dual port Distributed RAM (DRAM) on state-of-the-art Xilinx Virtex 7 series Field Programmable Gate Arrays (FPGA). Post place and route results for different configurations showed that the proposed design consumes much less memory, facilitating multiple engines on a single chip whilst maintaining a very low overall power profile. |
| ArticleNumber | 106612 |
| Author | Fahad, Muhammad Khan, Bilal Muhammad Beard, Cory Young, Rupert C.D. Bilal, Rabia Zaidi, Syed Sajjad Haider |
| Author_xml | – sequence: 1 givenname: Muhammad surname: Fahad fullname: Fahad, Muhammad organization: Department of Electronics and Power Engineering, National University of Sciences and Technology (NUST), Pakistan – sequence: 2 givenname: Bilal Muhammad surname: Khan fullname: Khan, Bilal Muhammad email: bmkhan@pnec.nust.edu.pk organization: Department of Electronics and Power Engineering, National University of Sciences and Technology (NUST), Pakistan – sequence: 3 givenname: Rabia surname: Bilal fullname: Bilal, Rabia organization: Department of Electrical Engineering, Usman Institute of Technology, Pakistan – sequence: 4 givenname: Rupert C.D. surname: Young fullname: Young, Rupert C.D. organization: Department of Engineering and Design, School of Engineering and Informatics, University of Sussex, UK – sequence: 5 givenname: Cory surname: Beard fullname: Beard, Cory organization: Computer Science and Electrical Engineering Department, University of Missouri-Kansas-City, USA – sequence: 6 givenname: Syed Sajjad Haider surname: Zaidi fullname: Zaidi, Syed Sajjad Haider organization: Department of Electronics and Power Engineering, National University of Sciences and Technology (NUST), Pakistan |
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| SubjectTerms | Algorithms Bit vector Electronic devices Field programmable gate arrays IP (Internet Protocol) IP lookup Multibillion packet per second Next generation network Packet classification Random access memory |
| Title | Multibillion packet lookup for next generation networks |
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