FPGA Implementation of ML, ZF and MMSE Equalizers for MIMO Systems

This paper presents an FPGA implementation of Maximum likelihood (ML), zero forcing (ZF) and minimum mean squared error (MMSE) equalizers applied to wireless multi-input multi-output (MIMO) systems with no fewer receive than transmit antennas. In spite of much prior work on this subject, we reveal s...

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Published inProcedia computer science Vol. 73; pp. 226 - 233
Main Authors Trimeche, Abdessalem, Sakly, Anis, Mtibaa, Abdellatif
Format Journal Article
LanguageEnglish
Published Elsevier B.V 2015
Subjects
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ISSN1877-0509
1877-0509
DOI10.1016/j.procs.2015.12.022

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Abstract This paper presents an FPGA implementation of Maximum likelihood (ML), zero forcing (ZF) and minimum mean squared error (MMSE) equalizers applied to wireless multi-input multi-output (MIMO) systems with no fewer receive than transmit antennas. In spite of much prior work on this subject, we reveal several new and surprising analytical results in terms of output signal-to-noise ratio (SNR), by comparing the Bit Error Rate (BER) and the average detection time consuming. Results based on the platform of Xilinx Virtex 6. We discuss the case where there a multiple transmit antennas and multiple receive antennas resulting in the formation of a Multiple Input Multiple Output (MIMO) channel with Zero Forcing equalizer, MIMO with MMSE equalizer, MIMO with ZF Successive Interference Cancellation equalizer, MIMO with ML equalization, MIMO with MMSE SIC and optimal ordering.
AbstractList This paper presents an FPGA implementation of Maximum likelihood (ML), zero forcing (ZF) and minimum mean squared error (MMSE) equalizers applied to wireless multi-input multi-output (MIMO) systems with no fewer receive than transmit antennas. In spite of much prior work on this subject, we reveal several new and surprising analytical results in terms of output signal-to-noise ratio (SNR), by comparing the Bit Error Rate (BER) and the average detection time consuming. Results based on the platform of Xilinx Virtex 6. We discuss the case where there a multiple transmit antennas and multiple receive antennas resulting in the formation of a Multiple Input Multiple Output (MIMO) channel with Zero Forcing equalizer, MIMO with MMSE equalizer, MIMO with ZF Successive Interference Cancellation equalizer, MIMO with ML equalization, MIMO with MMSE SIC and optimal ordering.
Author Trimeche, Abdessalem
Sakly, Anis
Mtibaa, Abdellatif
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Cites_doi 10.1049/el:19990058
10.1109/DTIS.2012.6232979
10.1109/ReConFig.2013.6732293
10.1109/18.825818
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10.1109/TIT.2003.809594
10.1109/18.978730
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Keywords FPGA,QAM
MMSE
SNR
MIMO
ZF
BER
ML
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– reference: A.TRIMECHE, N. Boukid, A.SAKLY, A.MTIBAA, Performance Analysis of ZF and MMSE Equalizers for MIMO Systems, 7th International conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), 2012.
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– reference: T. L. Marzetta, “BLAST training: Estimating channel characteristics for high-capacity space-time wireless,” i n Proc. 37th Annu. Allerton Conf. Communications, Control, and Computing, Sept. 22-24, 1999.
– reference: B. Hassibi and B. M. Hochwald, “How much training is needed in multiple- antenna wireless links?,” IEEE. Trans. Inform. Theory, vol. 49, pp. 951-963, Apr. 2003.
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– reference: B. M. Hochwald and T. L. Marzetta, “Unitary space-time modulation for multiple-antenna communication in Rayleigh flat fading,” IEEE Trans. Inform. Theory, vol. 46, pp 543-564, Mar. 2000.
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SubjectTerms BER
FPGA,QAM
MIMO
MMSE
SNR
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Title FPGA Implementation of ML, ZF and MMSE Equalizers for MIMO Systems
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