FPGA Implementation of ML, ZF and MMSE Equalizers for MIMO Systems

This paper presents an FPGA implementation of Maximum likelihood (ML), zero forcing (ZF) and minimum mean squared error (MMSE) equalizers applied to wireless multi-input multi-output (MIMO) systems with no fewer receive than transmit antennas. In spite of much prior work on this subject, we reveal s...

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Bibliographic Details
Published inProcedia computer science Vol. 73; pp. 226 - 233
Main Authors Trimeche, Abdessalem, Sakly, Anis, Mtibaa, Abdellatif
Format Journal Article
LanguageEnglish
Published Elsevier B.V 2015
Subjects
BER
FPGA,QAM
MIMO
MMSE
SNR
FPGA,QAM
MMSE
SNR
MIMO
ZF
BER
ML
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ISSN1877-0509
1877-0509
DOI10.1016/j.procs.2015.12.022

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Summary:This paper presents an FPGA implementation of Maximum likelihood (ML), zero forcing (ZF) and minimum mean squared error (MMSE) equalizers applied to wireless multi-input multi-output (MIMO) systems with no fewer receive than transmit antennas. In spite of much prior work on this subject, we reveal several new and surprising analytical results in terms of output signal-to-noise ratio (SNR), by comparing the Bit Error Rate (BER) and the average detection time consuming. Results based on the platform of Xilinx Virtex 6. We discuss the case where there a multiple transmit antennas and multiple receive antennas resulting in the formation of a Multiple Input Multiple Output (MIMO) channel with Zero Forcing equalizer, MIMO with MMSE equalizer, MIMO with ZF Successive Interference Cancellation equalizer, MIMO with ML equalization, MIMO with MMSE SIC and optimal ordering.
ISSN:1877-0509
1877-0509
DOI:10.1016/j.procs.2015.12.022