MOS transistor modeling for low-voltage and low-power analog IC design
This paper covers the device modeling aspects of low-power analog CMOS circuit design. The fundamental limits constraining the design of low-power circuits are first recalled with an emphasis on the implications of supply voltage reduction. Biasing MOS transistors at very low current provides new fe...
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| Published in | Microelectronic engineering Vol. 39; no. 1; pp. 59 - 76 |
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| Main Authors | , |
| Format | Journal Article |
| Language | English |
| Published |
Elsevier B.V
01.12.1997
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| Online Access | Get full text |
| ISSN | 0167-9317 1873-5568 |
| DOI | 10.1016/S0167-9317(97)00167-6 |
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| Summary: | This paper covers the device modeling aspects of low-power analog CMOS circuit design. The fundamental limits constraining the design of low-power circuits are first recalled with an emphasis on the implications of supply voltage reduction. Biasing MOS transistors at very low current provides new features but requires dedicated models valid in all regions of operation including weak, moderate and strong inversion. The influence of low-current biasing on noise and matching are also discussed. The design process has to be supported by efficient and accurate circuit simulations. To this end, the EKV compact MOST model for circuit simulation is shortly presented. |
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| Bibliography: | SourceType-Scholarly Journals-2 ObjectType-Feature-2 ObjectType-Conference Paper-1 content type line 23 SourceType-Conference Papers & Proceedings-1 ObjectType-Article-3 |
| ISSN: | 0167-9317 1873-5568 |
| DOI: | 10.1016/S0167-9317(97)00167-6 |