Low cost design of microprocessor EDAC circuit

An optimization method of error detection and correction（EDAC） circuit design is proposed. The method involves selecting or constructing EDAC codes of low cost hardware, associated with operation scheduling implementation based on 2-input XOR gates structure, and two actions for reducing hardware ce...

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Bibliographic Details
Published inJournal of semiconductors Vol. 36; no. 11; pp. 88 - 92
Main Author 郝丽 于立新 彭和平 庄伟
Format Journal Article
LanguageEnglish
Published Chinese Institute of Electronics 01.11.2015
Subjects
Circuit design
Circuits
Costs
DAC电路
Delay
EDAC
error detection and correction
Hardware
hardware implementation
Low cost
microprocessor
Microprocessors
Semiconductors
single-event upsets
微处理器
成本低
电路设计
硬件实现
编码电路
错误检测
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ISSN1674-4926
DOI10.1088/1674-4926/36/11/115005

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Summary:An optimization method of error detection and correction（EDAC） circuit design is proposed. The method involves selecting or constructing EDAC codes of low cost hardware, associated with operation scheduling implementation based on 2-input XOR gates structure, and two actions for reducing hardware cells, which can reduce the delay penalties and area costs of the EDAC circuit effectively. The 32-bit EDAC circuit hardware implementation is selected to make a prototype, based on the 180 nm process. The delay penalties and area costs of the EDAC circuit are evaluated. Results show that the time penalty and area cost of the EDAC circuitries are affected with different parity-check matrices and different hardware implementation for the EDAC codes with the same capability of correction and detection code. This method can be used as a guide for low-cost radiation-hardened microprocessor EDAC circuit design and for more advanced technologies.
Bibliography:Hao Li,Yu Lixin,Peng Heping,Zhuang Wei（ Beijing Microelectronic Technology Institute, Beijing 100076, China）
11-5781/TN
An optimization method of error detection and correction（EDAC） circuit design is proposed. The method involves selecting or constructing EDAC codes of low cost hardware, associated with operation scheduling implementation based on 2-input XOR gates structure, and two actions for reducing hardware cells, which can reduce the delay penalties and area costs of the EDAC circuit effectively. The 32-bit EDAC circuit hardware implementation is selected to make a prototype, based on the 180 nm process. The delay penalties and area costs of the EDAC circuit are evaluated. Results show that the time penalty and area cost of the EDAC circuitries are affected with different parity-check matrices and different hardware implementation for the EDAC codes with the same capability of correction and detection code. This method can be used as a guide for low-cost radiation-hardened microprocessor EDAC circuit design and for more advanced technologies.
error detection and correction; hardware implementation; microprocessor; single-event upsets
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ISSN:1674-4926
DOI:10.1088/1674-4926/36/11/115005