Effect of Topographical and Layout Factors on Gate CD Modeling for MOS Transistor Area

• Published in: IEEE transactions on semiconductor manufacturing Vol. 22; no. 2; pp. 290 - 296
• Main Authors: Izawa, M., Kurihara, M., Tanaka, J., Kawai, K., Yoshifuku, R., Maruyama, T., Fujiwara, N.
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.05.2009; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Applied sciences; Compact disks; Design. Technologies. Operation analysis. Testing; Electrodes; Electronics; Etching; Exact sciences and technology; Gate electrode; Gates (circuits); Integrated circuit modeling; Integrated circuits; Integrated circuits by function (including memories and processors); Lithography; Mathematical models; Microelectronic fabrication (materials and surfaces technology); MOS devices; MOSFETs; plasma etching; Process control; Production; Random access memory; Semiconductor device modeling; Semiconductor devices; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Semiconductors; shallow trench isolation; SRAM; SRAM chips; Static random access memory; Transistors; Static random access memory; Critical size; Trench technology; Process control; Random access memory; Polycrystal; MOS structure; Modeling; SRAM; Mean square error; Insulation technology; MOS devices; shallow trench isolation; ULSI circuit; Microelectronic fabrication; Reactive ion etching; Gate electrode; Plasma etching; Integrated circuit; MOS transistor; Root mean square value; Gates
• ISSN: 0894-6507; 1558-2345
• DOI: 10.1109/TSM.2009.2017639

The gate critical dimension (CD) variation of ultra-large-scale integrated circuit (ULSI) devices should be reduced to improve the production yield. An examination of the formulation of a gate-CD model for the transistor area, including the static random access memory (SRAM), was conducted taking the topographical and layout effects into account. It was found that the formulation of a gate CD for transistor areas with a root-mean-square error (RMSE) of less than 1 nm was efficient. The coefficients of the shallow-trench-isolation (STI) step height and polycrystalline-silicon (poly-Si) thickness were found to be inversely proportional to the distance between the gate electrodes. It was found that this dependence is related to the reactive-ion-etching (RIE) lag in the etching process.