Hierarchical interconnection structures for field programmable gate arrays

• Published in: IEEE transactions on very large scale integration (VLSI) systems Vol. 5; no. 2; pp. 186 - 196
• Main Authors: LAI, Y.-T, WANG, P.-T
• Format: Journal Article
• Language: English
• Published: Piscataway, NJ IEEE 01.06.1997; Institute of Electrical and Electronics Engineers
• Subjects: Applied sciences; Clustering algorithms; Computer architecture; Design. Technologies. Operation analysis. Testing; Electronics; Exact sciences and technology; Field programmable gate arrays; Integrated circuit interconnections; Integrated circuits; Logic arrays; Logic devices; Programmable logic arrays; Routing; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Switches; Wire; Theoretical study; Field programmable gate array; Interconnection; Computer aided design; Hierarchized structure; Integrated circuit
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/92.585219

Field programmable gate arrays (FPGA's) suffer from lower density and lower performance than conventional gate arrays. Hierarchical interconnection structures for field programmable gate arrays are proposed. They help overcome these problems. Logic blocks in a field programmable gate array are grouped into clusters. Clusters are then recursively grouped together. To obtain the optimal hierarchical structure with high performance and high density, various hierarchical structures with the same routability are discussed. The field programmable gate arrays with new architecture can be efficiently configured with existing computer aided design algorithms. The k-way min-cut algorithm is applicable to the placement step in the implementation. Global routing paths in a field programmable gate array can be obtained easily. The placement and global routing steps can be performed simultaneously. Experiments on benchmark circuits show that density and performance are significantly improved.