OMNI: A Framework for Integrating Hardware and Software Optimizations for Sparse CNNs

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems Vol. 40; no. 8; pp. 1648 - 1661
• Main Authors: Liang, Yun, Lu, Liqiang, Xie, Jiaming
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.08.2021; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Accelerator; Accelerators; Application specific integrated circuits; Artificial neural networks; Biological neural networks; Chips (memory devices); Circuit design; CNN; Convolution; Design; Design parameters; Field programmable gate arrays; FPGA; Hardware; Integrated circuit modeling; Integrated circuits; Kernel; Kernels; NAS; Neural networks; Object recognition; Optimization; Parallel processing; Pruning; Software; sparse; Sparsity; Synapses; Weight
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/TCAD.2020.3023903

Convolution neural networks (CNNs) as one of today's main flavor of deep learning techniques dominate in various image recognition tasks. As the model size of modern CNNs continues to grow, neural network compression techniques have been proposed to prune the redundant neurons and synapses. However, prior techniques disconnect the software neural networks compression and hardware acceleration, which fail to balance multiple design parameters, including sparsity, performance, hardware area cost, and efficiency. More concretely, prior unstructured pruning techniques achieve high sparsity at the expense of extra performance overhead, while prior structured pruning techniques relying on strict sparse patterns lead to low sparsity and extra hardware cost. In this article, we propose OMNI, a framework for accelerating sparse CNNs on hardware accelerators. The innovation of OMNI stems from that it uses hardware amenable on-chip memory partition patterns to seamlessly engage the software CNN model compression and hardware CNN acceleration. To accelerate the compute-intensive convolution kernel, a promising hardware optimization approach is memory partition, which divides the original weight kernels into several groups so that the different hardware processing elements can simultaneously access the weight. We exploit the memory partition patterns including block, cyclic, or hybrid as a means of CNN compression patterns. Our software CNN model compression balances the sparsity across different groups and our hardware accelerator employs hardware parallelization coordinately with the sparse patterns, leading to a desirable compromise between sparsity and performance. We further develop performance models to help the designers to quickly identify the pattern factors subject to an area constraint. Last, we evaluate our design on application specific integrated circuit (ASIC) and field-programmable gate array (FPGA) platform. Experiments demonstrate that OMNI achieves <inline-formula> <tex-math notation="LaTeX">3.4\times </tex-math></inline-formula>-<inline-formula> <tex-math notation="LaTeX">6.2\times </tex-math></inline-formula> speedup for the modern CNNs, over a comparably ideal dense CNN accelerator. OMNI shows <inline-formula> <tex-math notation="LaTeX">114.7\times </tex-math></inline-formula> energy efficiency improvement compared with GPU platform. OMNI is also evaluated on Xilinx ZC706 and ZCU102 FPGA platforms, achieving 41.5 GOP/s and 125.3 GOP/s, respectively.