A Reference-Waveform Oversampling Technique in a Fractional-N ADPLL

• Published in: IEEE journal of solid-state circuits Vol. 56; no. 11; pp. 3445 - 3457
• Main Authors: Du, Jianglin, Siriburanon, Teerachot, Hu, Yizhe, Govindaraj, Vivek, Staszewski, Robert Bogdan
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.11.2021; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithms; All-digital phase-locked loop (ADPLL); Analog to digital conversion; Analog to digital converters; Calibration; Circuits; Clocks; CMOS; Crystals; Digital to analog converters; Electric potential; fast settling; fractional-N; Jitter; low jitter; low power; Oscillators; Oversampling; Perturbation methods; Phase detectors; Phase locked loops; Power efficiency; reference-sampling PLL (RS-PLL); reference-waveform oversampling (ROS); successive approximation register analog-to-digital converter (SAR-ADC); Vibration; Voltage; Waveforms
• ISSN: 0018-9200; 1558-173X; 1558-173X
• DOI: 10.1109/JSSC.2021.3101046

This article presents a low-power fractional-<inline-formula> <tex-math notation="LaTeX">{N} </tex-math></inline-formula> all-digital phase-locked loop (ADPLL) employing a reference-waveform oversampling (ROS) phase detector (PD) that increases its effective rate four times, thus leading to lower jitter and settling time. The proposed ROS-PD adopts a bottom-plate sampling with a voltage zero-forcing technique, which yields high power efficiency and supports fractional phase compensation in the voltage domain through a programmable DAC. The PD output is then amplified by a low-noise gated amplifier and digitized by a low-power successive approximation register analog-to-digital converter (SAR-ADC). Leveraging the benefits of digital architecture, gain mismatches from the waveform estimator are calibrated by means of an LMS algorithm, consequently lowering fractional spurs. The proposed ADPLL is implemented in TSMC 28-nm LP CMOS. The prototype generates a 2.0-2.3-GHz carrier with an rms jitter of 414 fs while consuming only 1.15 mW. This corresponds to a state-of-the-art ADPLL FoM jitter of −247 dB in a fractional-<inline-formula> <tex-math notation="LaTeX">{N} </tex-math></inline-formula> mode. Due to the wide (largely linear) monotonic range and <inline-formula> <tex-math notation="LaTeX">4\times </tex-math></inline-formula> oversampling rate from a 48-MHz reference, without any additional circuitry, the proposed ADPLL can settle within <inline-formula> <tex-math notation="LaTeX">3~\mu \text{s} </tex-math></inline-formula> in face of a 70-MHz frequency step.