A 4.06 mW 10-bit 150 MS/s SAR ADC With 1.5-bit/cycle Operation for Medical Imaging Applications

• Published in: IEEE sensors journal Vol. 18; no. 11; pp. 4553 - 4560
• Main Authors: Sunny, Sharma, Yong Chen, Chirn Chye Boon
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.06.2018; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: 1.5-bit/cycle; ADC; Analog to digital conversion; Analog to digital converters; Biomedical imaging; capacitive digital-to-analog converter (CDAC); Capacitors; CMOS; Digital to analog conversion; Digital to analog converters; Error correction; Logic circuits; low power; Medical imaging; Noise levels; Redundancy; SAR; Sensors; successive approximation register; Switches; Voltage control
• ISSN: 1530-437X; 1558-1748
• DOI: 10.1109/JSEN.2018.2825400

This paper reports a 10-bit 150 MS/s successive approximation register analog-to-digital converter with binary-scaled redundancy-facilitated error correction technique. The proposed 1.5-bit/cycle technique with built-in capacitive digital-to-analog converter (CDAC) redundancy, corrects multiple erroneous decisions in a total of nine conversion cycles. The proposed binary-scaled redundancy provides a 12.5% error tolerance range for the incomplete CDAC voltage settling. The digital error-correction logic circuit presented uses a bit-overlap-and-add technique. The prototype chip was fabricated in 65-nm CMOS technology and occupies chip area of 0.038 mm 2 . It consumes 4.06 mW from a 1.2 V supply, achieving the Nyquist signal-to-noise-and-distortion ratio of 57.81 dB and the effective number of bits of 9.31-bit at an operating frequency of 150 MS/s, corresponding to the figure-of-merit of 42.6 fJ/ conversion-step.